參數(shù)資料
型號: LTC3829IFE#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING REGULATOR, PDSO38
封裝: 4.4 MM, LEAD FREE, PLASTIC, TSSOP-38
文件頁數(shù): 25/40頁
文件大?。?/td> 478K
代理商: LTC3829IFE#PBF
LTC3829
3829f
applicaTions inForMaTion
Fault Conditions: Current Limit and Current Foldback
The LTC3829 includes current foldback to help limit load
current when the output is shorted to ground. If the out-
put falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from its
maximumprogrammedvaluetoone-thirdofthemaximum
value. Foldback current limiting is disabled during the
soft-start or tracking up. Under short-circuit conditions
with very low duty cycles, the LTC3829 will begin cycle
skipping in order to limit the short-circuit current. In this
situation the bottom MOSFET will be dissipating most of
the power but less than in normal operation. The short
circuit ripple current is determined by the minimum on-
time tON(MIN) of the LTC3829 (≈90ns), the input voltage
and inductor value:
I
t
V
L
L SC
ON MIN
IN
( )
(
)
=
The resulting short-circuit current is:
I
V
R
I
SC
SENSE MAX
SENSE
L SC
=
1 3
1
2
3
/
(
)
( )
Phase-Locked Loop and Frequency Synchronization
The LTC3829 has a phase-locked loop (PLL) comprised of
aninternalvoltage-controlledoscillator(VCO)andaphase
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the PLLIN pin. The turn-on of the
second phases’ top MOSFETs is thus 120° out of phase
with the external clock and so on. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
Theoutputofthephasedetectorisapairofcomplementary
current sources that charge or discharge the internal filter
network. There is a precision 10A of current flowing out
of FREQ pin. This allows the user to use a single resistor to
SGNDtosettheswitchingfrequencywhennoexternalclock
is applied to the PLLIN pin. The internal switch between
the FREQ pin and the integrated PLL filter network is on,
allowing the filter network to be pre-charged at the same
voltage as of the FREQ pin. The relationship between the
voltage on the FREQ pin and operating frequency is shown
in Figure 15 and specified in the Electrical Characteristics
table. If an external clock is detected on the PLLIN pin, the
internal switch mentioned above turns off and isolates the
influence of the FREQ pin. Note that the LTC3829 can only
be synchronized to an external clock whose frequency is
within range of the LTC3829’s internal VCO. This is guar-
anteed to be between 250kHz and 770kHz. A simplified
block diagram is shown in Figure 16.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor CLP holds the voltage.
Typically, the external clock (on the PLLIN pin) input high
threshold is 1.6V, while the input low threshold is 1V.
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