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參數(shù)資料
| 型號： | LTC3823IGN#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 4 A SWITCHING CONTROLLER, PDSO28 |
| 封裝： | 0.150 INCH, LEAD FREE, PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 24/26頁 |
| 文件大小： | 302K |
| 代理商： | LTC3823IGN#TRPBF |
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LTC3823
7
3823fd
PIN FUNCTIONS (UH/GN)
VRNG (Pin 1/Pin 5): Sense Voltage Range Input. The volt-
age at this pin is ten times the nominal sense voltage at
maximum output current and can be set from 0.5V to 2V
by a resistive divider from INTVCC. The nominal sense
voltage defaults to 50mV when this pin is tied to ground
and 200mV when tied to INTVCC. Do not set this voltage
between 0.5V to ground and 2V to INTVCC.
VFB (Pin 2/Pin 6): Error Amplier Feedback Input. This pin
connects the error amplier input to an external resistive
divider from VOUT.
ITH (Pin 3/Pin 7): Current Control Threshold and Error
Amplier Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V with 0.75V corresponding to zero
sense voltage (zero current).
SGND (Pin 4/Pin 8): Signal Ground. All small-signal
components and compensation components should
connect to this ground, which in turn, connects to PGND
at one point.
ION (Pin 5/Pin 9): On-Time Current Input. Tie a resistor
from this pin to ground to set the one-shot timer current
and thereby, set the switching frequency.
VDIFFOUT (Pin 6/Pin 10): Output of Remote Sensing Dif-
ferential Amplier. Connect this to VFB directly or through
a resistive divider.
VOUTSENSE+ (Pin 8/Pin 11): This is the positive sense pin
for the remote sense differential amplier. Connect this pin
to the positive terminal of the output load capacitor.
VOUTSENSE– (Pin 9/Pin 12): This is the negative sense pin
for the remote sense differential amplier. Connect this pin
to the negative terminal of the output load capacitor.
NC (Pins 7, 10, UH Package): No Connect.
TRACK/SS (Pin 11/Pin 13): Output Voltage Tracking and
Soft-Start Input. When the IC is congured to be the
master of two outputs, a capacitor to ground at this pin
sets the ramp rate for the output voltage. When the IC is
congured to be the slave of two outputs, the VFB voltage
of the master IC is reproduced by a resistive divider and
applied to this pin during the soft-start phase. An internal
1.7μA soft-start current is charging this pin during the
soft-start phase.
PLLFLTR (Pin 12/Pin 14): The phase-locked loop’s lowpass
lter is tied to this pin. The voltage at this pin defaults to
1.180V when the IC is not synchronized with an external
clock at the PLLIN pin.
PLLIN (Pin 13/Pin 15): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with a 50k resistor.
VIN (Pin 14/Pin 16): Main Input Supply. Decouple this to
PGND with a capacitor (0.1μF to 1μF).
VINSNS (Pin 15, UH Package): VIN Voltage Sense Input.
Normally this pin is tied to VIN. However, in certain ap-
plications when the IC is powered from a separate supply,
VINSNS is tied to the upper MOSFET supply to sense the
VIN voltage. This pin is co-bonded with VIN in the GN
package.
ZVCC (Pin 16/Pin 17): Post-Package Zener Trim Supply.
Under normal conditions this pin should always be con-
nected to INTVCC.
Z1/SSENABLE (Pin 17/Pin 18): Post-Package Zener Trim
Control. This pin is a multifunctional pin used in produc-
tion for post-package trimming and tracking. Ground this
pin under normal soft-start operation. Connecting this
pin to INTVCC will turn off the soft-start current during
tracking.
Z2 (Pin 18/Pin 19): Post-Package Zener Trim Control.
This pin is used in production for post-package trimming.
Ground this pin under normal operation.
INTVCC (Pin 19/Pin 20): Internal 5V Regulated Output. The
control circuits are powered from this voltage. Decouple
this pin to PGND with a minimum of 4.7μF low ESR tan-
talum or ceramic capacitor.
DRVCC (Pin 20, UH Package): Driver Voltage Input. Must
be connected to INTVCC externally. Do not exceed 7V at
this pin. This pin is co-bonded to INTVCC internally in the
GN package.
BG (Pin 21/Pin 21): Bottom Gate Driver Output. This pin
drives the gate of the bottom N-channel MOSFET between
ground and INTVCC.
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