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參數資料
| 型號： | LTC3816EFE#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, PDSO38 |
| 封裝： | LEAD FREE, PLASTIC, TSSOP-38 |
| 文件頁數： | 22/44頁 |
| 文件大小： | 753K |
| 代理商： | LTC3816EFE#PBF |
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LTC3816
3816f
applicaTions inForMaTion
VRFREQ (V)
0
100
f OSC
(kHz)
200
300
400
500
0.6
1.2
1.8
2.4
3816 F16
600
700
0.3
0.9
1.5
2.1
SYNCHRONIZATION
FREE
RUNNING
Figure 16. VCO Transfer Curve
10A current source pull-up. Placing a resistor between
RFREQ and GND creates a potential given by the follow-
ing equation:
VRFREQ = IRFREQ RRFREQ
whereIRFREQ=10Aandallowstheoscillatorfree-running
frequency to be programmed between 210kHz to 580kHz
as shown in Figure 16.
An internal phase-locked loop (PLL) allows the LTC3816
to synchronize the internal oscillator to an external clock.
When there is a clocking signal at the MODE/SYNC pin, the
LTC3816phasedetectoradjuststheinternalPLLVCOinput,
synchronizingtheswitchingfrequencytotheexternalclock
frequency, and aligning the TG falling edge to the external
clock’s falling edge. During synchronization, the oscillator
frequency range widens to 120kHz to 650kHz.
For rapid frequency lock-in, the VCO input voltage can be
pre-biased to the desired operating frequency before the
external clock is applied. A resistor connected between
the RFREQ pin and GND can pre-bias the VCO’s input
voltage to the desired potential. Once pre-biased, the PLL
loop only needs to make slight changes to the VCO input
voltage in order to synchronize. The ability to pre-bias the
loop filter allows the PLL to lock-in rapidly.
CLKEN#, OVF AND PWRGD
CLKEN# is an open-drain output used to enable the CPU’s
PLL.Uponpower-up,thisopen-drainpull-downisdisabled,
and CLKEN# is pulled high by an external resistor. During
the soft-start ramp, when the switcher output is 45mV
from the VBOOT voltage, the controller completes its soft-
start cycle and 75s later, CLKEN# pulls low to enable the
processor PLL as shown in Figure 2.
At any instant, if the switcher output voltage rises above
the OVF threshold, the PWRGD pulls low, the regulator
output voltage is actively ramped to 0V and PWRGD
remains latched low until either the power is cycled or
VRON toggles. In the IMVP-6 configuration, the maximum
OVF threshold is 1.7V. In the IMVP-6.5 configuration, the
maximum threshold reduces to 1.55V.
The PWRGD pin is an open-drain output that indicates the
regulator output voltage has stabilized. At start-up, once
theswitcheroutputhassettledtoitsVIDpotentialformore
than 10ms, this open-drain releases and is pulled high by
theexternalpull-upresistor.Itpullslowagainiftheswitcher
output voltage remains outside of the +175mV/–270mV
window around its nominal VID set point for more than
750s. Once pulled low, the PWRGD state is latched and
the control logic initiates a shutdown sequence. After the
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