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參數(shù)資料
| 型號： | LTC3808 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit Bus Transceiver With 3-State Outputs 48-TVSOP -40 to 85 |
| 中文描述： | 無檢測電阻低EMI，同步DC / DC控制器的輸出跟蹤 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 372K |
| 代理商： | LTC3808 |
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7
LTC3808
3808f
PIU
PLLLPF (Pin 1/Pin 2):
Frequency Set/PLL Lowpass Filter.
When synchronizing to an external clock, this pin serves
as the low pass filter point for the phase-locked loop.
Normally, a series RC is connected between this pin and
ground.
When not synchronizing to an external clock, this pin serves
as the frequency select input. Tying this pin to GND selects
300kHz operation; tying this pin to V
IN
selects 750kHz
operation. Floating this pin selects 550kHz operation.
Connect a 2.2nF capacitor between this pin and GND and
a 1000pF capacitor between this pin and the SYNC/MODE
when using spread spectrum modulation operation.
SYNC/MODE (Pin 2/Pin 3):
This pin performs four func-
tions: 1) auxiliary winding feedback input, 2) external
clock synchronization input for phase-locked loop, 3)
Burst Mode, pulse skipping or forced continuous mode
select, and 4) enable
spread spectrum
modulation opera-
tion in pulse skipping mode. Applying a clock with fre-
quency between 250kHz to 750kHz causes the internal
oscillator to phase-lock to the external clock and disables
Burst Mode operation but allows pulse skipping at low
load currents.
To select Burst Mode operation at light loads, tie this pin
to V
IN
. Grounding this pin selects forced continuous
operation, which allows the inductor current to reverse.
Tying this pin to V
FB
selects pulse skipping mode. In these
cases, the frequency of the internal oscillator is set by the
voltage on the PLLLPF pin. Tying to a voltage between
1.35V to V
IN
– 0.5V enables spread spectrum modulation
operation. In this case, an internal 2.6
μ
A pull-down cur-
rent source helps to set the voltage at this pin by tying a
resistor with appropriate value between this pin and V
IN
.
Do not leave this pin floating
.
TRACK/SS (Pin 3/Pin 4):
Tracking Input for the Controller
or Optional External Soft-Start Input. This pin allows the
start-up of V
OUT
to “track” the external voltage at this pin
using an external resistor divider. Tying this pin to V
IN
allows V
OUT
start-up with the internal 1ms soft-start
clamp. An external soft-start can be programmed by
connecting a capacitor between this pin and ground.
Do
not leave this pin floating
.
(DFN/SSOP)
PGOOD (Pin 4/Pin 5):
Power Good Output Voltage Moni-
tor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on the feedback pin V
FB
is not within
±
13.3% of its nominal set point.
V
FB
(Pin 5/Pin 6):
Feedback Pin. This pin receives the
remotely sensed feedback voltage for the controller from
an external resistor divider across the output.
I
TH
(Pin 6/Pin 7):
Current Threshold and Error Amplifier
Compensation Point. Nominal operating range on this pin
is from 0.7V to 2V. The voltage on this pin determines the
threshold of the main current comparator.
RUN (Pin 7/Pin 8):
Run Control Input. Forcing this pin
below 1.1V shuts down the chip. Driving this pin to V
IN
or
releasing this pin enables the chip to start-up either by
tracking the external voltage at the TRACK/SS pin or with
the internal/external soft-start, all based on the connection
at the TRACK/SS pin.
IPRG (Pin 8/Pin 10):
Three-State Pin to Select Maximum
Peak Sense Voltage Threshold. This pin selects the maxi-
mum allowed voltage drop between the SENSE
+
and
SENSE
–
or SW pins (i.e., the maximum allowed drop
across the sense resistor or the external P-channel
MOSFET). Tie to V
IN
, GND or float to select 204mV, 85mV
or 125mV respectively.
BG (Pin 9/Pin 11):
Bottom (NMOS) Gate Drive Output.
This pin drives the gate of the external N-channel MOSFET.
This pin has an output swing from GND to SENSE
+
.
TG (Pin 10/Pin 12):
Top (PMOS) Gate Drive Output. This
pin drives the gate of the external P-channel MOSFET. This
pin has an output swing from GND to SENSE
+
.
SENSE
+
(Pin 11/Pin 13):
Positive Input to Differential
Current Comparator. Also powers the gate drivers. Nor-
mally connected to the source of the external P-channel
MOSFET when the sense resistor is not used. Otherwise,
it is connected to the sense resistor.
V
IN
(Pin 12/Pin 14):
Chip Signal Power Supply. This pin
powers the entire chip except for the gate drivers. Exter-
nally filtering this pin with a lowpass RC network (e.g.,
R = 10
, C = 1
μ
F) is suggested to minimize noise pickup,
especially in high load current applications.
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| LTC3808EDE#PBF | 功能描述:IC REG CTRLR BUCK PWM CM 14-DFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:96% 電源電壓:4 V ~ 36 V 降壓:無 升壓:是 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:24-WQFN 裸露焊盤 包裝:帶卷 (TR) |
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