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參數(shù)資料
| 型號(hào)： | LTC3766IUFD#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 316 kHz SWITCHING FREQ-MAX, PQCC28 |
| 封裝： | 4 X 5 MM, LEAD FREE, PLASTIC, MO-220, QFN-28 |
| 文件頁數(shù)： | 7/60頁 |
| 文件大?。?/td> | 607K |
| 代理商： | LTC3766IUFD#TRPBF |
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LTC3766
15
3766f
OPERATION
In general, the active clamp MOSFET is switched in a
complimentary fashion to the main primary-side MOSFET.
SincetheactiveclampMOSFETisaPMOS,theactiveclamp
gatedriver(AG)andthemainprimary-sidegatedriver(PG)
voltages are therefore “in-phase,” with a programmable
overlap time set by the LTC3765 DELAY pin.
The delay time between the active clamp PMOS turn-off
and the primary switch NMOS turn-on is critical for opti-
mizing efficiency. When the active clamp is on, the drain
of the primary NMOS, or primary switch node (SWP), is
driven to a voltage of approximately VIN/(1–D) by the main
transformer. When the active clamp turns off, the current
in the magnetizing inductance of the transformer ramps
this voltage linearly down to VIN. Power loss is minimized
by turning on the primary switch when the SWP voltage
is at a minimum. A resistor from the LTC3765 DELAY pin
to ground sets a fixed time for the PG turn-on delay.
The delay time between the primary switch turn-off and
the active clamp turn-on is substantially less critical.
When the primary switch turns off, the main transformer
leakage inductance is biased with the peak current of the
inductor reflected through the transformer. This current
drives the voltage across the active clamp PMOS quickly
to 0V. Turning on the PMOS after this transition results in
minimal switching power loss. The LTC3765 active clamp
turn on delay is internally fixed to 180ns, which normally
achieveszerovoltageswitchingontheactiveclampPMOS.
Onthesecondaryside,theturn-ondelayoftheforwardgate
(FG) and synchronous gate (SG) MOSFETs are adjusted by
the FGD and SGD pins respectively. These delays are set
using resistors to GND so as to minimize the dead time
(when the load current is being carried by MOSFET body
diodes)whileavoidingshoot-throughwiththeprimary-side
MOSFETs. A shoot-through condition exists if either the
PG and SG gates, or the AG and FG gates are high at the
same time. Note that the SG MOSFET turn-on delay has
a minimum limit that is established by the falling edge of
the SW node. The SG pin will not go high until SW has
falling below 0.5V. Refer to Delay Resistor Selection in
the Applications Information Section for more detailed
information. In standalone mode (100k or 50k resistor on
MODE) the dead time between PG and SG is set adaptively
to prevent shoot-through.
Frequency Setting and Synchronization
TheLTC3766usesasinglepintosettheoperatingfrequency
or to synchronize the internal oscillator to a reference
clock using and on-chip phase-locked loop (PLL). The
FS/SYNC pin sources a 20μA current, and it may be tied
to VCC for fixed 275kHz operation or have a single resistor
to GND to set the switching frequency to fSW = 4RFS. If a
clock signal (>2V) is detected at the FS pin, the LTC3766
will automatically synchronize to the falling edge of this
signal using an internal PLL.
Current Limit and Inductor Ripple Cancellation
Since the LTC3766 utilizes peak current control, the peak
inductor current is limited when the load current demand
increasesabovethecurrentlimitsetpoint.Thepeakcurrent
limit is established by an internal clamp on the maximum
level of the ITH voltage. The average current, however,
will be less than the peak current by an amount equal to
one-halfoftheinductorripplecurrent.Duringcurrentlimit,
this ripple current will change significantly with variations
in VIN, VOUT and switching frequency. Without inductor
ripple cancellation, this variation in ripple current would
also result in an average output current that changes
significantly, even though the peak current is held at a
constant value.
Inordertokeeptheaveragecurrentapproximatelyconstant
during current limit, the LTC3766 cancels the effect of the
ripple current by adjusting the value of the peak current
limit (or ITH clamp level) in proportion to the amount of
inductor ripple current. This is achieved by generating an
internal ramp that mimics the inductor current ramp, and
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| LTC3766MPGN#PBF | 功能描述:IC CONTROLLER SYNCH 28SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:Direct Flux Limit™, PolyPhase® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| LTC3766MPGN#TRPBF | 功能描述:IC CONTROLLER SYNCH 28SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:Direct Flux Limit™, PolyPhase® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
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| LTC3770EG | 制造商:Linear Technology 功能描述:LDO Cntrlr SYNC BUCK REG 0.6V to 32V 28-Pin SSOP |
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