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| 型號(hào)： | LTC3766HUFD#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 316 kHz SWITCHING FREQ-MAX, PQCC28 |
| 封裝： | 4 X 5 MM, LEAD FREE, PLASTIC, MO-220, QFN-28 |
| 文件頁數(shù)： | 26/60頁 |
| 文件大?。?/td> | 607K |
| 代理商： | LTC3766HUFD#TRPBF |
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LTC3766
32
3766f
APPLICATIONS INFORMATION
Estimating the Average Current Limit Accuracy
The accuracy of the average current limit depends on the
LTC3766 specifications together with a number of applica-
tioncircuitparametersaswellasparasitics.Consequently,
it is very difficult to precisely calculate the average current
limit accuracy. This accuracy can be estimated, however,
bycarefullyconsideringthethreeprimarysourcesoferror:
1. The accuracy of the current sense resistor and/or cur-
rent sense transformer. For resistor sensing, the accu-
racy of the current sense resistor is normally 1%. For
sense resistors less than 2mΩ, however, the parasitic
inductance can cause a significant error in the sensed
current. This error can be eliminated by adding an RC
filter as shown in Figure 11.
When using a current transformer, the accuracy of the
senseresistoronthecurrenttransformersecondaryand
the turns ratio of the transformers (both KCT and NP/
NS) are generally 1% or better. Depending on where the
current sense transformer is placed, however, there can
be an additional 1% to 4% error due to the magnetizing
current of both the main and current sense transform-
ers. Generally, this error is in the form of a relatively
constantoffset,anditcanbeadjustedoutforaparticular
design for nominal input voltage and maximum load
current. The resulting tolerance due to the variation in
magnetizing current effects is generally less than 2%,
resulting in an overall accuracy of approximately 3%
for current transformer sensing.
2. The accuracy of the average current sense threshold
VIS(AVG). The accuracy of the LTC3766 current sense
threshold is given in the Electrical Characteristics table
anddependsonthecurrentsensemodechosen.Current
transformer mode provides an accuracy of 10% and is
more accurate than the resistor sense mode accuracy
of 15%.
3. The accuracy of the compensation for inductor ripple
current. The accuracy of the inductor ripple compensa-
tion depends both on the internal adjustment of VITH
as well as the tolerance of the output inductor itself.
For most application circuits, the ripple compensation
accuracy will be 25% or better for current transformer
mode, and 35% or better for resistor sense mode. Note
that the inductor current ripple is typically 30% to 60%
of the average current limit, and only one-half of this
peak-to-peak ripple is being compensated. As a result,
the effect of the ripple compensation accuracy on the
average current limit is attenuated by a factor of:
FR =
R
+ 2
where R is the ratio of the peak-to-peak inductor ripple
current to the average current limit. For 30% to 60%
ripple, for example, the value of FR varies from 0.13 to
0.23.
Considering each of the above factors, the worst-case
tolerance of the average current limit can be estimated as:
IAVG = 3% + 10% + 0.23 (25%) = 18.5%
for current transformer mode and:
IAVG = 1% + 15% + 0.23 (35%) = 24%
for resistor sense mode. Since the three sources of error
are statistically independent, the current limit tolerance for
current transformer and resistance sense modes can be
calculated using the RSS method as approximately 12%
and 17% respectively.
Setting the Gate Drive Delays
The forward switch gate driver (FG) and the synchronous
switch gate driver (SG) operate with make-before-break
timing on the FG rising edge, and with simultaneous tim-
ing on the SG rising edge. The delays for these transitions
relative to the switching of the primary-side MOSFETs are
critical for optimizing efficiency, and can be configured
independently using the SGD and FGD pins.
The SG rising delay should be adjusted to minimize the
switch node (SW) body diode conduction. At full load, the
power loss in the body diode is significant, and the SG
rising delay can have a substantial impact on efficiency.
By minimizing the dead time between PG falling and SG
rising (while avoiding shoot-through), this power loss
is also minimized. Similarly, the dead time between SG
falling (set by the FG rising delay) and PG rising should
also be minimized.
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