參數(shù)資料
型號(hào)： LTC3736EGN
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： Dual 2-Phase, No RSENSE Synchronous Controller with Output Tracking
中文描述： 1 A DUAL SWITCHING CONTROLLER, 825 kHz SWITCHING FREQ-MAX, PDSO24
封裝： 0.150 INCH, PLASTIC, SSOP-24
文件頁(yè)數(shù)： 19/28頁(yè)
文件大小： 372K
代理商： LTC3736EGN
19
LTC3808
3808f
Table 2. The States of the PLLLPF Pin
PLLLPF PIN
SYNC/MODE PIN
FREQUENCY
0V
Floating
V
IN
RC Loop Filter Clock Signal
DC Voltage (<1.2V or V
IN
)
DC Voltage (<1.2V or V
IN
)
DC Voltage (<1.2V or V
IN
)
300kHz
550kHz
750kHz
Phase-Locked
to External Clock
Spread Spectrum
460kHz to 635kHz
Filter Caps
DC Voltage (>1.35V and <V
IN
– 0.5V)
Auxiliary Winding Control Using SYNC/MODE Pin
The SYNC/MODE pin can be used as an auxiliary feedback
to provide a means of regulating a flyback winding output.
When this pin drops below its ground-referenced 0.4V
threshold, continuous mode operation is forced.
During continuous mode, current flows continuously in
the transformer primary side. The auxiliary winding draws
current only when the bottom synchronous N-channel
MOSFET is on. When primary load currents are low and/
or the V
IN
/V
OUT
ratio is close to unity, the synchronous
MOSFET may not be on for a sufficient amount of time to
transfer power from the output capacitor to the auxiliary
load. Forced continuous operation will support an auxil-
iary winding as long as there is a sufficient synchronous
MOSFET duty factor. The SYNC/MODE input pin removes
the requirement that power must be drawn from the
transformer primary side in order to extract power from
the auxiliary winding. With the loop in continuous mode,
the auxiliary output may nominally be loaded without
regard to the primary output load.
The auxiliary output voltage V
AUX
is normally set, as
shown in Figure 8, by the turns ratio N of the transformer:
V
AUX
= (N + 1) V
OUT
nominally 200kHz to 1MHz. This is guaranteed, over
temperature and process variations, to be between 250kHz
and 750kHz. A simplified block diagram is shown in
Figure 7.
If the external clock frequency is greater than the internal
oscillator’s frequency, f
OSC
, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f
OSC
, current is sunk continuously, pulling down the
PLLLPF pin. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage on the PLLLPF pin is adjusted until
the phase and frequency of the internal and external
oscillators are identical. At the stable operating point, the
phase detector output is high impedance and the filter
capacitor C
LP
holds the voltage.
The loop filter components, C
LP
and R
LP
, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
= 10k and C
LP
is 2200pF to
0.01
μ
F.
Typically, the external clock (on SYNC/MODE pin) input
high level is 1.6V, while the input low level is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
APPLICATIU
W
U
U
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
2.4V
R
LP
C
LP
3808 F07
PLLLPF
EXTERNAL
OSCILLATOR
SYNC/
MODE
Figure 7. Phase-Locked Loop Block Diagram
LTC3808
+
+
R6
R5
1
μ
F
V
OUT
V
AUX
C
OUT
L1
1:N
SYNC/MODE
BG
SW
TG
3808 F08
V
IN
Figure 8. Auxiliary Output Loop Connection
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