參數(shù)資料
型號(hào)： LTC3727IG-1#TR
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： 3 A SWITCHING CONTROLLER, 580 kHz SWITCHING FREQ-MAX, PDSO28
封裝： 5.30 MM, PLASTIC, SSOP-28
文件頁(yè)數(shù)： 10/32頁(yè)
文件大?。?/td> 366K
代理商： LTC3727IG-1#TR
18
LTC3727/LTC3727-1
3727fc
than 7.5V. This can be done with the inductive boost
winding as shown in Figure 6.
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors CB connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor CB in the functional diagram is charged though
external diode DB from INTVCC when the SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the CB voltage across the gate-source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: VBOOST =
VIN + VINTVCC. The value of the boost capacitor CB needs
to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the exter-
nal Schottky diode must be greater than VIN(MAX). When
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and the
input current decreases, then the efficiency has improved.
If there is no change in input current, then there is no
change in efficiency.
Figure 6. Secondary Output Loop & EXTVCC Connection
Output Voltage
The LTC3727 output voltages are each set by an external
feedback resistive divider carefully placed across the
output capacitor. The resultant feedback signal is
compared with the internal precision 0.800V voltage
reference by the error amplifier. The output voltage is
given by the equation:
VV
R
OUT =+
08
1
2
1
.
where R1 and R2 are defined in Figure 2.
SENSE+/SENSE– Pins
The common mode input range of the current comparator
sense pins is from 0V to 14V. Continuous linear operation
is guaranteed throughout this range allowing output volt-
age setting from 0.8V to 14V. A differential NPN input
stage is biased with internal resistors from an internal
2.4V source as shown in the Functional Diagram. This
requires that current either be sourced or sunk from the
SENSE pins depending on the output voltage. If the output
voltage is below 2.4V current will flow out of both SENSE
pins to the main output. The output can be easily preloaded
by the VOUT resistive divider to compensate for the current
comparator’s negative input bias current. The maximum
current flowing out of each pair of SENSE pins is:
ISENSE+ + ISENSE– = (2.4V – VOUT)/24k
Since VOSENSE is servoed to the 0.8V reference voltage, we
can choose R1 in Figure 2 to have a maximum value to
absorb this current.
Rk
V
VV
MAX
OUT
124
08
24
()
.
.–
=
for VOUT < 2.4V
APPLICATIO S I FOR ATIO
WU
UU
EXTVCC
FCB
SGND
VIN
TG1
SW
BG1
PGND
LTC3727
RSENSE
VOUT
VSEC
+
COUT
+
1
μF
3727 F06
N-CH
R6
+
CIN
VIN
T1
1:N
OPTIONAL EXTVCC
CONNECTION
7.5V < VSEC < 8.5V
R5
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