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參數(shù)資料
| 型號： | LTC3672BEDC-1#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 172K |
| 描述： | IC REG TRPL BCK/LINEAR 8-DFN |
| 標準包裝： | 2,500 |
| 拓撲： | 降壓（降壓）同步（1），線性（LDO）（2） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 3 |
| 頻率 - 開關： | 2.25MHz |
| 電壓/電流 - 輸出 1： | 1.8V，400mA |
| 電壓/電流 - 輸出 2： | 1.2V，150mA |
| 電壓/電流 - 輸出 3： | 2.8V，150mA |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 無 |
| 電源電壓： | 2.9 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 8-DFN（2x2） |
| 包裝： | 帶卷 (TR) |
LTC3672B-1
7
3672B1f
OPERATION
INTRODUCTION
The LTC3672B-1 combines a synchronous buck converter
with two low dropout linear DC regulators (LDOs) to
provide three low voltage outputs from a higher volt-
age input source. All outputs are enabled and disabled
together through the ENALL pin. The output regulation
voltages are set during manufacturing to 1.8V nominal
for the buck, 1.2V nominal for LDO1, and 2.8V nominal
for LDO2. LDO1 may be powered off of the buck output
for higher overall ef ciency.
For versions of the IC with different output regulation
voltages, consult the LTC factory.
SYNCHRONOUS BUCK REGULATOR
The synchronous buck uses a constant-frequency current
mode architecture, switching at 2.25MHz down to very light
loads, and supports no-load operation by skipping cycles.
When the input voltage drops very close to or falls below
the target output voltage, the buck supports 100% duty
cycle operation (low dropout mode). Soft-start circuitry
limits inrush current when powering on. Output current is
limited in the event of an output short-circuit. The switch
node is slew-rate limited to reduce EMI radiation. The
buck regulation control-loop compensation is internal to
the IC, and requires no external components.
Main Control Loop
An error ampli er monitors the difference between an
internal reference voltage and the voltage on the BUCKOUT
pin. When the BUCKOUT voltage is below the reference,
the error ampli er output voltage increases. When the
BUCKOUT voltage exceeds the reference, the error ampli-
er output voltage decreases.
The error ampli er output controls the peak inductor current
through the following mechanism: Paced by a free-running
2.25MHz oscillator, the main P-channel MOSFET switch is
turned on at the start of the oscillator cycle. Current ows
from the V
IN
supply through this PMOS switch, through
the inductor via the SW pin, and into the output capacitor
and load. When the current reaches the level programmed
by the output of the error ampli er, the PMOS is shut off,
and the N-channel MOSFET synchronous recti er turns
on. Energy stored in the inductor discharges into the load
through this NMOS. The NMOS turns off at the end of the
2.25MHz cycle, or sooner, if the current through it drops
to zero before the end of the cycle.
Through these mechanisms, the error ampli er adjusts the
peak inductor current to deliver the required output power
to regulate the output voltage as sensed by the BUCKOUT
pin. All necessary control-loop compensation is internal to
the step-down switching regulator, requiring only a single
ceramic output capacitor for stability.
Light Load/No-Load Cycle-Skipping
At light loads, the inductor current may reach zero before
the end of the oscillator cycle, which will turn off the NMOS
synchronous recti er. In this case, the SW pin goes high
impedance and will show damped ringing . This is known
as discontinuous operation, and is normal behavior for a
switching regulator. At very light load and no-load condi-
tions, the buck will automatically skip cycles as needed
to maintain output regulation.
Soft-Start
Soft-start in the buck regulator is accomplished by gradually
increasing the maximum allowed peak inductor current
over a 200約 period. This allows the output to rise slowly,
controlling the inrush current required to charge up the
output capacitor. A soft-start cycle occurs whenever the
LTC3672B-1 is enabled, or after a fault condition has oc-
curred (thermal shutdown or UVLO).
Switch Slew-Rate Control
The buck regulator contains new patent pending circuitry
to limit the slew rate of the switch node (SW pin). This
new circuitry is designed to transition the switch node
over a period of a couple nanoseconds, signi cantly
reducing radiated EMI and conducted supply noise while
maintaining high ef ciency.
LOW V
IN
SUPPLY UNDERVOLTAGE LOCKOUT
An undervoltage lockout (UVLO) circuit shuts down the
LTC3672B-1 when V
IN
drops below about 1.7V.
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