參數(shù)資料
型號(hào): LTC3547EDDB
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 0.7 A DUAL SWITCHING CONTROLLER, 2700 kHz SWITCHING FREQ-MAX, PDSO8
封裝: 3 X 2 MM, 0.75 MM HEIGHT, PLASTIC, M0-229WECD-1, DFN-8
文件頁數(shù): 3/16頁
文件大?。?/td> 296K
代理商: LTC3547EDDB
LTC3547
11
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APPLICATIO S I FOR ATIO
WU
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Efciency Considerations
The percent efciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efciency and which change would
produce the most improvement. Percent efciency can
be expressed as:
%Efciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four sources usually account for the losses in
LTC3547 circuits: 1) VIN quiescent current, 2) switching
losses, 3) I2R losses, 4) other system losses.
1) The VIN current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET
driver and control currents. VIN current results in a
small (<0.1%) loss that increases with VIN, even at
no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is a current out
of VIN that is typically much larger than the DC bias cur-
rent. In continuous mode, IGATECHG = fO(QT + QB), where
QT and QB are the gate charges of the internal top and
bottom MOSFET switches. The gate charge losses are
proportional to VIN and thus their effects will be more
pronounced at higher supply voltages.
3) I2R losses are calculated from the DC resistances of
the internal switches, RSW, and external inductor,
RL. In continuous mode, the average output current
ows through inductor L, but is “chopped” between
the internal top and bottom switches. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
RSW = (RDS(ON)TOP) (DC) + (RDS(ON)BOT) (1– DC)
(5)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. Thus, to obtain I2R losses:
I2R losses = IOUT2 (RSW + RL)
4) Other “hidden” losses, such as copper trace and in-
ternal battery resistances, can account for additional
efciency degradations in portable systems. It is very
important to include these “system” level losses in
the design of a system. The internal battery and fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and very low ESR at
the switching frequency. Other losses, including diode
conduction losses during dead-time, and inductor
core losses, generally account for less than 2% total
additional loss.
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