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參數(shù)資料
| 型號(hào)： | LTC3419IMS#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.2 A DUAL SWITCHING CONTROLLER, 2700 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封裝： | LEAD FREE, PLASTIC, MSOP-10 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 266K |
| 代理商： | LTC3419IMS#TRPBF |
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LTC3419
12
3419fa
The RDS(ON)forboththetopandbottomMOSFETscanbe
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
I2R losses = IOUT2 (RSW + RL)
4. Other “hidden” losses, such as copper trace and
internal battery resistances, can account for additional
efciency degradations in portable systems. It is very
important to include these “system” level losses in
the design of a system. The internal battery and fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and very low ESR at
the switching frequency. Other losses, including diode
conduction losses during dead-time, and inductor
core losses, generally account for less than 2% total
additional loss.
Thermal Considerations
In a majority of applications, the LTC3419 does not
dissipate much heat due to its high efciency. In the
unlikely event that the junction temperature somehow
reaches approximately 150°C, both power switches will be
turned off and the SW node will become high impedance.
The goal of the following thermal analysis is to determine
whether the power dissipated causes enough temperature
rise to exceed the maximum junction temperature (125°C)
of the part. The temperature rise is given by:
TRISE = PD θJA
Where PD is the power dissipated by the regulator and
θJA is the thermal resistance from the junction of the die
to the ambient temperature. The junction temperature,
TJ, is given by:
TJ = TRISE + TAMBIENT
As a worst-case example, consider the case when the
LTC3419 is in dropout on both channels at an input voltage
of 2.7V with a load current of 600mA and an ambient
temperature of 70°C. From the Typical Performance
Characteristics graph of Switch Resistance, the RDS(ON)
of the main switch is 0.6
Ω. Therefore, power dissipated
by each channel is:
PD = IOUT2 RDS(ON) = 216mV
Given that the thermal resistance of a properly soldered
DFN package is approximately 40°C/W, the junction
temperature of an LTC3419 device operating in a 70°C
ambient temperature is approximately:
TJ = (2 0.216W 40°C/W) + 70°C = 87.3°C
which is well below the absolute maximum junction
temperature of 125°C.
PC Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3419. These items are also illustrated graphically in the
layout diagrams of Figures 2 and 3. Check the following
in your layout:
1. Does the capacitor CIN connect to the power VIN (Pin 5)
and GND (Pin 9) as closely as possible? This capacitor
provides the AC current of the internal power MOSFETs
and their drivers.
2. Are the respective COUT and L closely connected? The
(–) plate of COUT returns current to GND and the (–)
plate of CIN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT1 and a ground sense line
terminated near GND (Pin 9). The feedback signals VFB1
and VFB2 should be routed away from noisy components
and traces, such as the SW lines (Pins 4 and 6), and
their trace length should be minimized.
4. Keep sensitive components away from the SW pins, if
possible. The input capacitor CIN and the resistors R1,
R2, R3 and R4 should be routed away from the SW
traces and the inductors.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at a single
point. These ground traces should not share the high
current path of CIN or COUT.
6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components. These copper areas should be
connected to VIN or GND.
APPLICATIONS INFORMATION
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