參數資料
型號: LTC3413
廠商: Linear Technology Corporation
英文描述: 3A, 2MHz Monolithic Synchronous Regulator for DDR/QDR Memory Termination
中文描述: 第3A,2MHz的單片同步調節(jié)器用于DDR / QDR存儲器終端
文件頁數: 11/16頁
文件大小: 243K
代理商: LTC3413
11
LTC3413
sn3413 3413fs
APPLICATIOU
125
°
C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
W
U
U
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to
I
LOAD
(ESR), where ESR is the effective series
resistance of C
OUT
.
I
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I
TH
pin external components and output capaci-
tor shown in Figure 1a will provide adequate compensa-
tion for most applications.
Output Voltage Tracking of V
REF
For applications in which the V
REF
pin is connected to the
V
IN
pin, the output voltage will be equal to one-half of the
voltage on the V
IN
pin. Because the output voltage will
track the input voltage, any disturbance on V
IN
will appear
on V
OUT
. For example, a load step transient could cause
the input voltage to drop if there is insufficient bulk
capacitance at the V
IN
pin. The corresponding drop in the
output voltage during the load step transient is caused by
the V
OUT
tracking of V
IN
and should not be confused with
poor load regulation.
Design Example
As a design example, consider using the LTC3413 in an
application with the following specifications: V
IN
= 2.5V,
V
OUT
= 1.25V, I
OUT(MAX)
=
±
3A, f = 1MHz.
First, calculate the timing resistor:
R
k
k
OSC
=
=
3 23 10
1 10
10
313
11
6
.
Use a standard value of 309k. Next, calculate the inductor
value for about 40% ripple current:
L
V
1 2
MHz
1
A
V
V
H
=
=
μ
1 25
.
1
1 25
2 5
.
0 47
.
.
Using a 0.47
μ
H inductor results in a maximum ripple
current of:
=
μ
=
I
V
MHz
1
H
V
V
A
L
1 25
.
0 47
1
1 25
2 5
.
1 33
.
.
C
OUT
will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100
μ
F ceramic capacitors will be used. C
IN
should be sized
for a maximum current rating of:
I
A
V
V
V
V
A
RMS
RMS
=
=
3
1 25
2 5
.
2 5
1 25
.
1
1 5
.
.
.
Decoupling the PV
IN
pins with two 100
μ
F capacitors is
相關PDF資料
PDF描述
LTC3413EFE 3A, 2MHz Monolithic Synchronous Regulator for DDR/QDR Memory Termination
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