參數(shù)資料
型號: LTC3388EDD-3#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 0.21 A SWITCHING REGULATOR, PDSO10
封裝: 3 X 3 MM, LEAD FREE, PLASTIC, MO-229WEED-2, DFN-10
文件頁數(shù): 20/20頁
文件大小: 282K
代理商: LTC3388EDD-3#PBF
LTC3388-1/LTC3388-3
9
338813f
PIN FUNCTIONS
EN (Pin 1): Enable Input. Logic level input referenced to
VIN2. A logic high on EN will enable the buck converter.
Driving EN to VIN2 will result in no additional quiescent
current on VIN. However, if EN is driven near VIH or VIL
40nA of additional quiescent current can appear on VIN.
STBY (Pin 2): Standby Input. Logic level input referenced
to VIN2. A logic high on STBY will place the part in standby
mode. Driving STBY to VIN2 will result in no additional
quiescent current on VIN. However, if STBY is driven near
VIH or VIL 40nA of additional quiescent current can ap-
pear on VIN.
CAP (Pin 3): Internal rail referenced to VIN to serve as gate
drive for buck PMOS switch. A 1μF capacitor should be
connected between CAP and VIN. This pin is not intended
for use as an external system rail.
VIN (Pin 4): Input Voltage. A 2.2μF or larger capacitor
should be connected from VIN to GND.
SW (Pin 5): Switch Pin for the Buck Switching Regulator.
A 22μH or larger inductor should be connected from SW
to VOUT.
VOUT (Pin 6): Sense pin used to monitor the output volt-
age and adjust it through internal feedback.
VIN2 (Pin 7): Internal low voltage rail to serve as gate drive
for buck NMOS switch. Also serves as a logic high rail for
output voltage select bits D0 and D1. A 4.7μF capacitor
should be connected from VIN2 to GND. This pin is not
intended for use as an external system rail.
D1 (Pin 8): Output Voltage Select Bit. D1 should be tied
high to VIN2 or low to GND to select desired VOUT (see
Table 1).
D0 (Pin 9): Output Voltage Select Bit. D0 should be tied
high to VIN2 or low to GND to select desired VOUT (see
Table 1).
PGOOD (Pin 10): Power Good Open-Drain NMOS Output.
The PGOOD pin is Hi-Z when VOUT is above 92% of the
target value.
GND (Exposed Pad Pin 11): Ground. The exposed pad
should be connected to a continuous ground plane on the
second layer of the printed circuit board by several vias
directly under the LTC3388-1/LTC3388-3.
相關PDF資料
PDF描述
LTC3388IDD-1#PBF 0.21 A SWITCHING REGULATOR, PDSO10
LTC3388IMSE-1#PBF 0.21 A SWITCHING REGULATOR, PDSO10
LTC3388EDD-1#PBF 0.21 A SWITCHING REGULATOR, PDSO10
LTC3388IMSE-3#TRPBF 0.21 A SWITCHING REGULATOR, PDSO10
LTC3388EDD-1#TRPBF 0.21 A SWITCHING REGULATOR, PDSO10
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