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參數資料
| 型號： | LTC2914IDHC-1#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封裝： | 5 X 3 MM, PLASTIC, MO-229WJED-1, DFN-16 |
| 文件頁數： | 4/16頁 |
| 文件大小： | 211K |
| 代理商： | LTC2914IDHC-1#TR |
LTC2914
12
2914fa
At VCC = 1V, the weak pull-up current on OV is barely turned
on. Therefore, an external pull-up resistor of no more than
100k is recommended on the OV pin if the state and pull-up
strength of the OV pin is crucial at very low VCC.
Note however, by adding an external pull-up resistor, the
pull-up strength on the OV pin is increased. Therefore, if
it is connected in a wired-OR connection, the pull-down
strength of any single device must accommodate this
additional pull-up strength.
Output Rise and Fall Time Estimation
The UV and OV outputs have strong pull-down capabil-
ity. The following formula estimates the output fall time
(90% to 10%) for a particular external load capacitance
(CLOAD):
tFALL ≈ 2.2 RPD CLOAD
where RPD is the on-resistance of the internal pull-down
transistor, typically 50Ω at VCC > 1V and at room tem-
perature (25°C). CLOAD is the external load capacitance
on the pin. Assuming a 150pF load capacitance, the fall
time is 16.5ns.
The rise time on the UV and OV pins is limited by a 400k
pull-up resistance to VCC. A similar formula estimates the
output rise time (10% to 90%) at the UV and OV pins:
tRISE ≈ 2.2 RPU CLOAD
where RPU is the pull-up resistance.
OV Latch (LTC2914-1)
With the LATCH pin held low, the OV pin latches low when
an OV condition is detected. The latch is cleared by raising
the LATCH pin high. If an OV condition clears while LATCH
is held high, the latch is bypassed and the OV pin behaves
the same as the UV pin with a similar timeout period at the
output. If LATCH is pulled low while the timeout period is
active, the OV pin latches as before.
Disable (LTC2914-2)
The LTC2914-2 allows disabling the UV and OV outputs
via the DIS pin. Pulling DIS high forces both outputs to
remain weakly pulled high, regardless of any faults that
occur on the inputs. However, if a UVLO condition oc-
curs, UV asserts and pulls low, but the timeout function
is bypassed. UV pulls high as soon as the UVLO condition
is cleared.
DIS has a weak 2μA (typical) internal pull-down current
guaranteeing normal operation with the pin left open.
APPLICATIONS INFORMATION
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| LTC2914IGN-1#TR | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
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| LTC2914HGN-1#TR | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| LTC2927CDDB#TRM | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
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