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參數(shù)資料
| 型號(hào)： | LTC2911CTS8-4#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | LEAD FREE, PLASTIC, MO-193, TSOT-23, 8 PIN |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 245K |
| 代理商： | LTC2911CTS8-4#TRPBF |
LTC2911
13
2911f
Resistor Selection for Combined Reset
and Power-Fail Divider
When the power-fail and reset signals are based on the
same supply, the PFI and ADJ inputs may be connected
to a single resistive divider formed from three resistors.
The configuration is shown in Figure 4. For a given bias
current I, RA, RB and RC can be calculated from:
RA =
0.5V
I
RB =RA
VTRIP_PFI_FALL
VTRIP_ ADJ
– 1
RC =RA
VTRIP_ ADJ
0.5V
– 1
VTRIP_PFI_FALL
VTRIP_ ADJ
For example, consider monitoring a 5V, ±5% supply with
VTRIP_PFI_FALL = 4.5V and VTRIP_ADJ = 4V. The resulting
VTRIP_PFI_RISEisequalto4.63Vor3%aboveVTRIP_PFI_FALL.
The maximum VTRIP_PFI_RISE should not overlap the mini-
mum power supply voltage level for PFO to deassert when
the supply recovers. Mathematically, after factoring in the
sum of the power supply tolerance and the LTC2911 toler-
ance, the VTRIP_PFI_RISE should be lower than 5V – 6.5%.
APPLICATIONS INFORMATION
See Threshold Accuracy section for more details. In the
design, if we wish to consume about 5A in the divider,
RA = 100k. We then find RB = 12.4k and RC = 787k (nearest
1% standard values).
Setting the Reset Timeout
RST goes high after the V1, V2 and ADJ inputs are above
their thresholds for a reset timeout period. Connecting
the TMR pin to V1 enables the internal 200ms timer.
To configure a different reset timeout period connect a
capacitor between the TMR pin and ground.
The following formula approximates the value of capacitor
needed for a particular timeout:
CTMR = tRST 106.5 [pF/ms]
Leaving the TMR pin open with no external capacitor
generates a reset timeout of approximately 400s. Larger
capacitors may be used to increase the timeout, but the
capacitor leakage current must not exceed 500nA. Other-
wise, the timer accuracy will be severely affected.
Suitable values of CTMR for a given tRST may be selected
from Figure 5.
–
+
–
+
+–
0.5V
2911 F04
PFI
ADJ
LTC2911
RB
RC
RA
VTRIP
Figure 4. Combining PFI/ADJ Monitoring of One Supply
with Three Resistors
Figure 5. External Timeout vs CTMR
CTMR (F)
10p
0.1
EXTERNAL
TIMEOUT
,t
RST
(ms)
10
10000
100p
1n
10n
100n
1
2911 F05
1
100
1000
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