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參數(shù)資料
| 型號： | LTC2911CDDB-4#TRM |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | 3 X 2 MM, PLASTIC, MO-229, DFN-8 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 245K |
| 代理商： | LTC2911CDDB-4#TRM |
LTC2911
14
2911f
APPLICATIONS INFORMATION
Reset Latch Mode
At any time, the TMR pin can be pulled low to latch the
RST pin status, overriding the reset operation. This feature
is useful when testing a system at supply voltages that
might otherwise cause the RST pin to assert.
If the RST pin is unasserted (high) before the latch is
enabled (by pulling the TMR pin low), RST will remain
unasserted after the TMR pin is released. This is true
provided that all reset monitor inputs are valid when TMR
releases, regardless of their state while the TMR pin was
low. However, if RST was unasserted before TMR was
pulled low, and now one of the inputs is invalid when TMR
is released, RST will assert after a tPL,LRpropagation delay
(see Figure 6a). Conversely, if RST was asserted (low)
LATCH RELEASE
TMR
ADJ, V1, V2
t > tSU,MON
VTMR(LATCH)
VRTX
VTMR(LATCH) + VTMR
1.0V
2911 F06a
tP,LR
RST
Figure 6a. Input Toggled Low While Timer Latched.
RST Goes Low tP,LR After Latch Release
TMR
LATCH RELEASE
VRTX
1.0V
2911 F06b
t > tSU,MON
tRST
ADJ, V1, V2
VTMR(LATCH)
VTMR(LATCH) +
VTMR
Figure 6b. Input Toggled High While Timer Latched.
RST Goes High tRST After Latch Release
TMR
tRST
1.0V
2911 F06c
t < tRST
VTRM(LATCH)
VRTX
RST
ADJ, V1, V2
LATCH RELEASE
VTMR(LATCH) +
VTMR
Figure 6c. Timer Latched Before Timeout. After Latch Release,
RST Stays Low for a Full Timeout Before Going High
TMR
VTRX
1.0V
t > tHD,MON
t > tSU,MON
2911 F06d
NO
RECOUNTING
tRST
t > tRST
ADJ, V1, V2
RST
VTRM(LATCH)
LATCH RELEASE
MARGINING
VTMR(LATCH)
+
VTMR
Figure 6d. Timer Latched After Timeout and RST High.
RST Stays High After Margining if Inputs are Restored
Before Release
before TMR was pulled low, and all inputs are valid when
TMR is released, RST will deassert (go high) after a tRST
delay (see Figures 6b and 6c). The RST pin remains as-
serted for a full tRST timeout after the TMR pin is released,
regardless of the state of the tRST timer before the latch
was enabled. The reset latch mode is useful for perform-
ing supply margining tests without resetting the system
(see Figure 6d).
At least 2.9A of pull-up or pull-down current is required
to hold the TMR pin high or low to configure the internal
timer or reset latch mode. However, during the timer mode
transition, 100A will be required to switch the TMR float-
ing state to ground or V1. Connecting the TMR pin to any
voltage other than ground or V1 may have unpredictable
results.
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