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參數(shù)資料
| 型號： | LTC2704IGW-12#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 18/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT QUAD VOUT 44-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | LTC275x 18-Bit DAC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 設(shè)置時(shí)間： | 8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-BSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 44-SSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | * |
LTC2704
5
2704fd
The
l denotes specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The notation V+ is used to denote both V+1 and V+2 when the same
voltage is applied to both pins.
Note 3: Guaranteed by design, not subject to test.
Note 4: Measured in unipolar 0V to 5V mode.
Note 5: When using SRO, maximum SCK frequency fMAX is limited by SRO
propagation delay as follows:
fMAX =
1
2t9 + tS
()
, where ts is the setup time of the receiving device.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CIN
Digital Input Capacitance
VIN = 0V (Note 3)
l
5pF
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD = 4.5V to 5.5V
t1
SDI Valid to SCK Setup
l
7ns
t2
SDI Valid to SCK Hold
l
7ns
t3
SCK High Time
l
11
ns
t4
SCK Low Time
l
11
ns
t5
CS/LD Pulse Width
l
9ns
t6
LSB SCK High to CS/LD High
l
0ns
t7
CS/LD Low to SCK Positive Edge
l
12
ns
t8
CS/LD High to SCK Positive Edge
l
12
ns
t9
SRO Propagation Delay
CLOAD = 10pF
l
18
ns
t10
CLR Pulse Width
l
50
ns
t11
LDAC Pulse Width
l
15
ns
t12
CLR Low to RFLAG Low
CLOAD = 10pF (Note 3)
l
50
ns
t13
CS/LD High to RFLAG High
CLOAD = 10pF (Note 3)
l
40
ns
SCK Frequency
50% Duty Cycle (Note 5)
l
40
MHz
VDD = 2.7V to 3.3V
t1
SDI Valid to SCK Setup
l
9ns
t2
SDI Valid to SCK Hold
l
9ns
t3
SCK High Time
l
15
ns
t4
SCK Low Time
l
15
ns
t5
CS/LD Pulse Width
l
12
ns
t6
LSB SCK High to CS/LD High
l
0ns
t7
CS/LD Low to SCK Positive Edge
l
12
ns
t8
CS/LD High to SCK Positive Edge
l
12
ns
t9
SRO Propagation Delay
CLOAD = 10pF
l
26
ns
t10
CLR Pulse Width
l
90
ns
t11
LDAC Pulse Width
l
20
ns
t12
CLR Low to RFLAG Low
CLOAD = 10pF
l
70
ns
t13
CS/LD High to RFLAG High
CLOAD = 10pF
l
60
ns
SCK Frequency
50% Duty Cycle (Note 5)
l
25
MHz
TIMING CHARACTERISTICS
ELECTRICAL CHARACTERISTICS The l denotes specications which apply over the full operating
temperature range, otherwise specications are TA = 25°C, V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx =
REFG1 = REFG2 = GND = 0V.
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