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參數(shù)資料
| 型號： | LTC2704CGW-16#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/22頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT QUAD VOUT 44-SSOP |
| 產(chǎn)品培訓模塊： | LTC275x 18-Bit DAC |
| 標準包裝： | 27 |
| 設置時間： | 10µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-BSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 44-SSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | * |
| 配用： | DC752A-B-ND - BOARD DAC LTC2704-16 |
LTC2704
16
2704fd
should be driven with a Thevenin-equivalent impedance
of 10kΩ or less. If not used, they should be shorted to
their respective signal grounds, AGNDx.
POWER-ON RESET AND CLEAR
When power is rst applied to the LTC2704, all DACs
power-up in 5V unipolar mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
are zero volts.
When the CLR pin is taken low, a system clear results. The
command and address shift registers, and the code and
conguration B2 buffers, are reset to 0; the DAC outputs
are all reset to zero volts. The B1 buffers are left intact, so
that any subsequent “Update B1→B2” command (includ-
ing the use of LDAC) restores the addressed DACs to their
respective previous states.
If CLR is asserted during an operation, i.e., when CS/LD
is low, the operation is aborted. Integrity of the relevant
input (B1) buffers is not guaranteed under these condi-
tions, therefore the contents should be checked using
readback or replaced.
The RFLAG pin is used as a ag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the logic supply VDD dips
below approximately 2V; and stays asserted until any valid
update command is executed.
SLEEP MODE
When a sleep command (C3 C2 C1 C0 = 1110) is issued,
the addressed DAC or DACs go into power-down mode.
DACs A and B share a reference inverting amplier as do
DACs C and D. If either DAC A or DAC B (similarly for DACs
C and D) is powered down, its shared reference inverting
amplier remains powered on. When both DAC A and DAC B
are powered down together, their shared reference invert-
ing amplier is also powered down (similarly for DACs C
and D). To determine the sleep status of a particular DAC,
a direct read span command is performed by addressing
the DAC and reading its status on the readback pin SRO.
The fth LSB is the sleep status bit (see Figures 2a and
2b). Table 4 shows the sleep status bit’s functionality.
Table 4. Readback Sleep Status Bit
SLP
STATUS
0
DAC n Awake
1
DAC n in Sleep Mode
OPERATION
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