For more information www.linear.com/LTC2641 applicaTions inForMaTion
參數(shù)資料
型號(hào)： LTC2641CDD-16#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 7/24頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT VOUT 8-DFN
產(chǎn)品培訓(xùn)模塊： Open Loop DAC
標(biāo)準(zhǔn)包裝： 121
設(shè)置時(shí)間： 1µs
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 600µW
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 8-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 8-DFN-EP（3x3）
包裝： 管件
輸出數(shù)目和類型： 1 電壓，單極
采樣率（每秒）： *
產(chǎn)品目錄頁(yè)面： 1352 (CN2011-ZH PDF)
LTC2641/LTC2642
15
26412fc
For more information www.linear.com/LTC2641
applicaTions inForMaTion
Unbuffered Operation and VOUT Loading
The DAC output is available directly at the VOUT pin, which
swings from GND to VREF. Unbuffered operation provides
thelowestpossibleoffset,full-scaleandlinearityerrors,the
fastest settling time and minimum power consumption.
However, unbuffered operation requires that appropriate
loading be maintained on the VOUT pin. The LTC2641/
LTC2642 VOUT can be modeled as an ideal voltage source
in series with a source resistance of ROUT, typically 6.2k
(Figure 4). The DAC’s linear output impedance allows it
to drive medium loads (RL > 60k) without degrading INL
or DNL; only the gain error is increased. The gain error
(GE) caused by a load resistance, RL, (relative to full
scale) is:
GE =
–1
1+
ROUT
RL
In 16-bit LSBs:
GE = –65536
1+
ROUT
RL
LSB
ROUT has a low tempco (typically < ±50ppm/°C), and is
independent of DAC code. The variation of ROUT, part-to-
part, is typically less than ±20%.
Note on LSB units:
For the following error descriptions, “LSB” means 16-bit
LSB and 65,536 is rounded to 66k.
To convert to 14-bit LSBs (LTC2641-14/LTC2642-14)
divide by 4.
To convert to 12-bit LSBs (LTC2641-12/LTC2642-12)
divide by 16.
A constant current, IL, loading VOUT will produce an
offset of:
VOFFSET = –IL ROUT
For VREF = 2.5V, a 16-bit LSB equals 2.5V/65,536, or 38V.
Since ROUT is 6.2k, an IL of 6nA produces an offset of
1LSB. Therefore, to avoid degrading DAC performance,
it is critical to protect the VOUT pin from any sources of
leakage current.
Unbuffered VOUT Settling Time
The settling time at the VOUT pin can be closely approxi-
mated by a single-pole response where:
t = ROUT (COUT + CL)
(Figure 4). Settling to 1/2LSB at 16-bits requires about 12
time constants (ln(2 65,536)). The typical settling time
of 1s corresponds to a time constant of 83ns, and a
total (COUT + CL) of about 83ns/6.2k = 13pF. The internal
capacitance, COUT is typically 10pF, so an external CL of
3pF corresponds to 1s settling to 1/2LSB.
IL
VOUT
0V TO VREF
ROUT
VOUT
COUT
LTC2641
LTC2642
VREF
REF
GND
CODE
2N
VREF
( )
CL
26412 F04
RL
+
–
Figure 4. VOUT Pin Equivalent Circuit
Op Amp Selection
The optimal choice for an external buffer op amp depends
on whether the DAC is used in the unipolar or bipolar
mode of operation, and also depends on the accuracy,
speed, power dissipation and board area requirements of
the application. The LTC2641/LTC2642’s combination of
tiny package size, rail-to-rail single supply operation, low
power dissipation, fast settling and nearly ideal accuracy
specifications makes it impractical for one op amp type
to fit every application.
In bipolar mode (LTC2642 only), the amplifier operates
with the internal resistors to provide bipolar offset and
scaling. In this case, a precision amplifier operating from
dual power supplies, such as the the LT1678 provides the
±VREF output range (Figure 3).
In unipolar mode, the output amplifier operates as a unity
gain voltage follower. For unipolar, single supply applica-
tions a precision, rail-to-rail input, single supply op amp
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