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參數(shù)資料
| 型號： | LTC2626 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 18-Bit Universal Bus Driver With 3-State Outputs 56-BGA MICROSTAR JUNIOR -40 to 85 |
| 中文描述： | 16/14/12軌到軌DAC的具有I2C接口 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 310K |
| 代理商： | LTC2626 |
3
LTC2606/LTC2616/LTC2626
26061626f
ELECTRICAL C
temperature range, otherwise specifications are at T
A
= 25
°
C. REF = 4.096V (V
CC
= 5V), REF = 2.048V (V
CC
= 2.7V), V
OUT
unloaded,
unless otherwise noted. (Note 11)
HARA TERISTICS
The
●
denotes specifications which apply over the full operating
SYMBOL
PSR
R
OUT
PARAMETER
Power Supply Rejection
DC Output Impedance
CONDITIONS
V
CC
=
±
10%
V
REF
= V
CC
= 5V, Midscale; –15mA
≤
I
OUT
≤
15mA
V
REF
= V
CC
= 2.7V, Midscale; –7.5mA
≤
I
OUT
≤
7.5mA
●
V
CC
= 5.5V, V
REF
= 5.5V
Code: Zero Scale; Forcing Output to V
CC
Code: Full Scale; Forcing Output to GND
V
CC
= 2.7V, V
REF
= 2.7V
Code: Zero Scale; Forcing Output to V
CC
Code: Full Scale; Forcing Output to GND
MIN
TYP
–81
0.05
0.06
MAX
UNITS
dB
●
0.15
0.15
I
SC
Short-Circuit Output Current
●
●
15
15
34
36
60
60
mA
mA
●
●
7.5
7.5
22
29
50
50
mA
mA
Reference Input
Input Voltage Range
Resistance
Capacitance
Reference Current, Power Down Mode
Power Supply
V
CC
Positive Supply Voltage
I
CC
Supply Current
●
0
V
CC
160
V
Normal Mode
●
88
124
15
0.001
k
pF
μ
A
I
REF
DAC Powered Down
●
1
For Specified Performance
V
CC
= 5V (Note 3)
V
CC
= 3V (Note 3)
DAC Powered Down (Note 3) V
CC
= 5V
DAC Powered Down (Note 3) V
CC
= 3V
●
2.7
5.5
0.5
0.4
1
1
V
●
●
●
●
0.340
0.27
0.35
0.10
mA
mA
μ
A
μ
A
Digital I/O (Note 11)
V
IL
Low Level Input Voltage
(SDA and SCL)
High Level Input Voltage
(SDA and SCL)
Low Level Input Voltage (LDAC)
●
–0.5
0.3V
CC
V
V
IH
(Note 8)
●
0.7V
CC
V
V
IL(LDAC)
V
CC
= 4.5V to 5.5V
V
CC
= 2.7V to 5.5V
V
CC
= 2.7V to 5.5V
V
CC
= 2.7V to 3.6V
See Test Circuit 1
●
●
0.8
0.6
V
V
V
V
V
V
IH(LDAC)
High Level Input Voltage (LDAC)
●
●
2.4
2.0
V
IL(CAn)
Low Level Input Voltage on CAn
(n= 0, 1, 2)
High Level Input Voltage on CAn
(n= 0, 1, 2)
Resistance from CAn(n= 0, 1, 2)
to V
CC
to Set CAn= V
CC
Resistance from CAn(n= 0, 1, 2)
to GND to Set CAn= GND
Resistance from CAn(n= 0, 1, 2)
to V
CC
or GND to Set CAn= Float
Low Level Output Voltage
Output Fall Time
●
0.15V
CC
V
IH(CAn)
See Test Circuit 1
●
0.85V
CC
V
R
INH
See Test Circuit 2
●
10
k
R
INL
See Test Circuit 2
●
10
k
R
INF
See Test Circuit 2
●
2
M
V
OL
t
OF
Sink Current = 3mA
V
O
= V
IH(MIN)
to V
O
= V
IL(MAX)
,
C
B
= 10pF to 400pF (Note 9)
●
●
20 + 0.1C
B
0
0.4
250
V
ns
t
SP
Pulse Width of Spikes Suppressed
by Input Filter
Input Leakage
I/O Pin Capacitance
Capacitive Load for Each Bus Line
External Capacitive Load on Address
Pins CAn(n= 0, 1, 2)
●
0
50
ns
I
IN
C
IN
C
B
C
CAX
0.1V
CC
≤
V
IN
≤
0.9V
CC
●
1
μ
A
pF
pF
pF
●
10
400
10
●
●
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