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參數(shù)資料
| 型號： | LTC2624IGN-1#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT QUAD R-R 16-SSOP |
| 標準包裝： | 100 |
| 設(shè)置時間： | 7µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 10mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 1351 (CN2011-ZH PDF) |
LTC2604/LTC2614/LTC2624
14
2604fd
OPERATION
2600 F03
INPUT CODE
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
32,768
0
65,535
INPUT CODE
OUTPUT
VOLTAGE
VREF = VCC
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
(b)
(a)
(c)
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The ampliers’ DC output
impedance is 0.025Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30Ω 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The ampliers are stable driving capacitive loads of up
to 1000pF.
Board Layout
The excellent load regulation and DC crosstalk performance
of these devices is achieved in part by keeping “signal”
and “power” grounds separate.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin functions as a return path for power sup-
ply currents in the device and should be connected to
analog ground. Resistance from the GND pin to system
star ground should be as low as possible. When a zero
scale DAC output voltage of zero is desired, the REFLO pin
(pin 2) should be connected to system star ground.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown in
Figure 3b. Similarly, limiting can occur near full scale when
the REF pins are tied to VCC. If REF x = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 3c. No full-scale
limiting can occur if REF x is less than VCC – FSE.
Offset and linearity are dened and tested over the region
of the DAC transfer function where no output limiting
can occur.
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