參數(shù)資料
型號: LTC2621CDD
廠商: Linear Technology
文件頁數(shù): 7/16頁
文件大?。?/td> 0K
描述: IC DAC 12BIT SGL R-R VOUT 10DFN
標(biāo)準(zhǔn)包裝: 121
設(shè)置時(shí)間: 7µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 1.88mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 10-DFN(3x3)
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極
采樣率(每秒): *
LTC2601/LTC2611/LTC2621
15
2601fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
3.00
±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38
± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65
± 0.10
(2 SIDES)
0.75
±0.05
R = 0.115
TYP
2.38
±0.10
(2 SIDES)
1
5
10
6
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD10) DFN 1103
0.25
± 0.05
2.38
±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65
±0.05
(2 SIDES)
2.15
±0.05
0.50
BSC
0.675
±0.05
3.50
±0.05
PACKAGE
OUTLINE
0.25
± 0.05
0.50 BSC
PACKAGE DESCRIPTION
Figure 3. Effects of Rail-to-Rail Operation On the DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
2601 F03
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
32, 768
0
65, 535
INPUT CODE
OUTPUT
VOLTAGE
(a)
VREF = VCC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
OPERATION
DD Package
10-Lead Plastic DFN (3mm
× 3mm)
(Reference LTC DWG # 05-08-1699)
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