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參數資料
| 型號： | LTC2620CUFD#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC OCTAL R-R 12BIT 20-QFN |
| 標準包裝： | 73 |
| 設置時間： | 70µs |
| 位數： | 12 |
| 數據接口： | 串行 |
| 轉換器數目： | 8 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 20mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 20-QFN 裸露焊盤（5x4） |
| 包裝： | 管件 |
| 輸出數目和類型： | 8 電壓，單極 |
| 采樣率（每秒）： | * |
| 產品目錄頁面： | 1351 (CN2011-ZH PDF) |
LTC2600/LTC2610/LTC2620
12
2600fe
OPERATION
Power-On Reset
The LTC2600/LTC2610/LTC2620 clear the outputs to
zero-scale when power is rst applied, making system
initialization consistent and repeatable.
Forsomeapplications,downstreamcircuitsareactiveduring
DAC power-up, and may be sensitive to nonzero outputs
from the DAC during this time. The LTC2600/2610/2620
contain circuitry to reduce the power-on glitch: the analog
outputs typically rise less than 10mV above zero-scale
during power on if the power supply is ramped to 5V in 1ms
or more. In general, the glitch amplitude decreases as the
power supply ramp time is increased. See Power-On Reset
Glitch in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the
range –0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 16) is in transition.
Transfer Function
The digital-to-analog transfer function is:
V
k
V
OUT IDEAL
N
REF
() =
2
where k is the decimal equivalent of the binary DAC
input code, N is the resolution and VREF is the voltage at
REF (Pin 6).
Serial Interface
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, powering on the SDI and
SCK buffers and enabling the input shift register. Data (SDI
input) is transferred at the next 24 rising SCK edges. The
4-bit command, C3-C0, is loaded rst; then the 4-bit DAC
address, A3-A0; and nally the 16-bit data word. The data
word comprises the 16-, 14- or 12-bit input code, ordered
MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits (LTC2600,
LTC2610 and LTC2620 respectively). Data can only be
transferred to the device when the CS/LD signal is low.The
rising edge of CS/LD ends the data transfer and causes the
device to carry out the action specied in the 24-bit input
word. The complete sequence is shown in Figure 2a.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The rst four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
While the minimum input word is 24 bits, it may optionally
be extended to 32 bits. To use the 32-bit word width, 8
don’t-care bits are transferred to the device rst, followed
by the 24-bit word as just described. Figure 2b shows the
Table 1.
COMMAND*
C3
C2
C1
C0
0000
Write to Input Register n
0001
Update (Power Up) DAC Register n
0010
Write to Input Register n, Update (Power Up) All n
0011
Write to and Update (Power Up) n
0100
Power Down n
1111
No Operation
*Command and address codes not shown are reserved and should not be used.
ADDRESS (n)*
A3
A2
A1
A0
0000
DAC A
0001
DAC B
0010
DAC C
0011
DAC D
0100
DAC E
0101
DAC F
0110
DAC G
0111
DAC H
1111
All DACs
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