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參數(shù)資料
| 型號： | LTC2616CDD |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface |
| 中文描述： | SERIAL INPUT LOADING, 9 us SETTLING TIME, 14-BIT DAC, PDSO10 |
| 封裝： | 3 X 3 MM, PLASTIC, MO-229WEED-2, DFN-10 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 310K |
| 代理商： | LTC2616CDD |
15
LTC2606/LTC2616/LTC2626
26061626f
OPERATIOU
C3
1ST DATA BYTE
Input Word (LTC2606)
Write Word Protocol for LTC2606/LTC2616/LTC1626
C2
C1
C0
X
X
X
X
D13
D14
D15
S
W
A
SLAVE ADDRESS
1ST DATA BYTE
D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 D0
A
2ND DATA BYTE
A
3RD DATA BYTE
A
P
2606 F03
2ND DATA BYTE
INPUT WORD
3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2616)
C2
C1
C0
X
X
X
X
D11
D12
D13
D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
2ND DATA BYTE
3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2626)
C2
C1
C0
X
X
X
X
D9
D10
D11
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
2ND DATA BYTE
3RD DATA BYTE
a high impedance state, and the output pin is passively
pulled to ground through 90k resistors. Input- and DAC-
register contents are not disturbed during power-down.
The DAC channel can be put into power-down mode by
using command 0100
b
. The 16-bit data word is ignored.
The supply and reference currents are reduced to almost
zero when the DAC is powered down; the effective
resistance at REF becomes a high impedance input
(typically > 1G
).
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 2
or performing an asychronous update (LDAC) as de-
scribed in the next section. The DAC is powered up as its
voltage output is updated. When the DAC in powered-
down state is powered up and updated, normal settling is
delayed. The main bias generation circuit block has been
Figure 3
automatically shut down in addition to the DAC amplifier
and reference input and so the power up delay time is
12
μ
s (for V
CC
= 5V) or 30
μ
s (for V
CC
= 3V)
Asynchronous DAC Update Using LDAC
In addition to the update commands shown in Table 2, the
LDAC pin asynchronously updates the DAC register with
the contents of the input register. Asynchronous update is
disabled when the input word is being clocked into the part.
If a complete input word has been written to the part, a low
on the LDAC pin causes the DAC register to be updated
with the contents of the input register.
If the input word is being written to the part, a low going
pulse on the LDAC pin before the completion of three bytes
of data powers up the DAC but does not cause the output
to be updated. If LDAC remains low after a complete input
word has been written to the part, then LDAC is recog-
nized, the command specified in the 24-bit word just
transferred is executed and the DAC output is updated.
The DAC is powered up when LDAC is taken low, indepen-
dent of any activity on the I
2
C bus.
If LDAC is low at the falling edge of the 9th clock of the 3rd
byte of data, it inhibits any software power-down com-
mand that was specified in the input word.
Table 2
COMMAND*
C3
C2
0
0
0
0
1
*Command codes not shown are reserved and should not be used.
C1
0
0
1
0
1
C0
0
1
1
0
1
0
0
0
1
1
Write to Input Register
Update (Power Up) DAC Register
Write to and Update (Power Up)
Power Down
No Operation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2616CDD-1 | 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface |
| LTC2606CDD | 18-Bit Universal Bus Driver With 3-State Outputs 56-SSOP -40 to 85 |
| LTC2606CDD-1 | 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface |
| LTC2616 | 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface |
| LTC2616IDD-1 | 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface |
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