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參數(shù)資料
| 型號： | LTC2615CGN-1 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP |
| 中文描述： | SERIAL INPUT LOADING, 9 us SETTLING TIME, 14-BIT DAC, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 317K |
| 代理商： | LTC2615CGN-1 |
10
LTC2605/LTC2615/LTC2625
2605f
Table 1.
COMMAND*
C3
C2
0
0
0
0
0
1
*Address and command codes not shown are reserved and should not be used.
C1
0
0
1
1
0
1
C0
0
1
0
1
0
1
0
0
0
0
1
1
Write to Input Register n
Update (Power Up) DAC Register n
Write to Input Register n, Update (Power Up) All n
Write to and Update (Power Up) n
Power Down n
No Operation
ADDRESS (n)*
A3
A2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
1
A1
0
0
1
1
0
0
1
1
1
A0
0
1
0
1
0
1
0
1
1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
All DACs
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and V
REF
is the voltage at REF
(Pin 6).
Serial Digital Interface
The LTC2605/LTC2615/LTC2625 communicate with a
host using the standard 2-wire digital interface. The
Timing Diagram (Figure 1) shows the timing relationship
of the signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources are required on these lines.
The value of these pull-up resistors is dependent on the
power supply and can be obtained from the I
2
C specifica-
tions. For an I
2
C bus operating in the fast mode, an active
pull-up will be necessary if the bus capacitance is greater
than 200pF.
The LTC2605/LTC2615/LTC2625 are receive-only (slave)
devices. The master can write to the LTC2605/LTC2615/
LTC2625. The LTC2605/LTC2615/LTC2625 do not
respond to a read from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while SCL
is high. The bus is then free for communication with
another I
2
C device.
OPERATIOU
Power-On Reset
The LTC2605/LTC2615/LTC2625 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2605-1/
LTC2615-1/LTC2625-1 set the voltage outputs to midscale
when power is first applied.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2605/
LTC2615/LTC2625 contain circuitry to reduce the
power-on glitch: the analog outputs typically rise less
than 10mV above zero scale during power on if the
power supply is ramped to 5V in 1ms or more. In general,
the glitch amplitude decreases as the power supply ramp
time is increased. See Power-On Reset Glitch in the
Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
–0.3V
≤
V
REF
≤
V
CC
+ 0.3V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V
CC
(Pin 16) is in transition.
Transfer Function
The digital-to-analog transfer function is
k
OUT IDEAL
N
2
V
V
REF
(
)
=
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