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參數(shù)資料
| 型號： | LTC2607CDE-1 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | 16-/14-/12-Bit Dual Rail-to-Rail DACs with I2C Interface |
| 中文描述： | SERIAL INPUT LOADING, 10 us SETTLING TIME, 16-BIT DAC, PDSO12 |
| 封裝： | 4 X 3 MM, EXPOSED PAD, PLASTIC, MO-229WGED, DFN-12 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 318K |
| 代理商： | LTC2607CDE-1 |
3
LTC2607/LTC2617/LTC2627
26071727f
ELECTRICAL C
temperature range, otherwise specifications are at T
A
= 25
°
C. REF = 4.096V (V
CC
= 5V), REF = 2.048V (V
CC
= 2.7V), REFLO = 0V,
V
OUT
unloaded, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
PSR
Power Supply Rejection
V
CC
±
10%
R
OUT
DC Output Impedance
V
REF
= V
CC
= 5V, Midscale;
–15mA
≤
I
OUT
≤
15mA
V
REF
= V
CC
= 2.7V, Midscale;
–7.5mA
≤
I
OUT
≤
7.5mA
DC Crosstalk (Note 4)
Due to Full Scale Output Change (Note 5)
Due to Load Current Change
Due to Powering Down (per channel)
I
SC
Short-Circuit Output Current
V
CC
= 5.5V, V
REF
= 5.5V
Code: Zero Scale; Forcing Output to V
CC
Code: Full Scale; Forcing Output to GND
V
CC
= 2.7V, V
REF
= 2.7V
Code: Zero Scale; Forcing Output to V
CC
Code: Full Scale; Forcing Output to GND
Reference Input
Input Voltage Range
Resistance
Normal Mode
Capacitance
I
REF
Reference Current, Power Down Mode
DAC Powered Down
Power Supply
V
CC
Positive Supply Voltage
For Specified Performance
I
CC
Supply Current
V
CC
= 5V (Note 3)
V
CC
= 3V (Note 3)
DAC Powered Down (Note 3) V
CC
= 5V
DAC Powered Down (Note 3) V
CC
= 3V
Digital I/O (Note 11)
V
IL
Low Level Input Voltage (SDA and SCL)
V
IH
High Level Input Voltage (SDA and SCL)
V
IL(LDAC)
Low Level Input Voltage (LDAC)
V
CC
= 4.5V to 5.5V
V
CC
= 2.7V to 5.5V
V
IH(LDAC)
High Level Input Voltage (LDAC)
V
CC
= 2.7V to 5.5V
V
CC
= 2.7V to 3.6V
V
IL(CAn)
Low Level Input Voltage on CAn
See Test Circuit 1
(n= 0, 1, 2)
V
IH(CAn)
High Level Input Voltage on CAn (n= 0, 1, 2)
See Test Circuit 1
R
INH
Resistance from CAn(n= 0, 1, 2)
See Test Circuit 2
to V
CC
to Set CAn= V
CC
R
INL
Resistance from CAn(n= 0, 1, 2)
See Test Circuit 2
to GND to Set CAn= GND
R
INF
Resistance from CAn(n= 0, 1, 2)
See Test Circuit 2
to V
CC
or GND to Set CAn= Float
V
OL
Low Level Output Voltage
Sink Current = 3mA
t
OF
Output Fall Time
V
O
= V
IH(MIN)
to V
O
= V
IL(MAX)
,
C
B
= 10pF to 400pF (Note 9)
t
SP
Pulse Width of Spikes Suppressed by Input Filter
I
IN
Input Leakage
0.1V
CC
≤
V
IN
≤
0.9V
CC
C
IN
I/O Pin Capacitance
Note 12
C
B
Capacitive Load for Each Bus Line
C
CAX
External Capacitive Load on Address
Pins CAn(n= 0, 1, 2)
HARA TERISTICS
The
●
denotes specifications which apply over the full operating
MIN
TYP
–
8
0
MAX
UNITS
dB
●
0.032
0.15
●
0.035
±
4
±
3
±
30
0.15
μ
V
μ
V/mA
μ
V
●
●
15
15
36
37
60
60
mA
mA
●
●
7.5
7.5
22
30
50
50
mA
mA
●
0
V
CC
8
0
V
●
44
64
30
k
pF
μ
A
●
0.001
1
●
2.7
5.5
1.3
1
1
1
V
●
●
●
●
0.66
0.52
0.4
0.10
mA
mA
μ
A
μ
A
●
0.3V
CC
V
V
V
V
V
V
V
●
0.7V
CC
●
●
0.
8
0.6
●
●
2.4
2.0
●
0.15V
CC
●
0.
8
5V
CC
V
●
10
k
●
10
k
●
2
M
●
●
20 + 0.1C
B
0
0.4
250
V
ns
●
0
50
1
10
400
10
ns
μ
A
pF
pF
pF
●
●
●
●
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