• 參數(shù)資料
    型號(hào): LTC2605CGN
    廠商: LINEAR TECHNOLOGY CORP
    元件分類: DAC
    英文描述: Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP
    中文描述: SERIAL INPUT LOADING, 10 us SETTLING TIME, 16-BIT DAC, PDSO16
    封裝: 0.150 INCH, PLASTIC, SSOP-16
    文件頁數(shù): 4/16頁
    文件大?。?/td> 317K
    代理商: LTC2605CGN
    4
    LTC2605/LTC2615/LTC2625
    2605f
    TIW
    range, otherwise specifications are at T
    A
    = 25
    °
    C. (See Figure 1) (Notes 8, 9)
    The
    denotes specifications which apply over the full operating temperature
    Note 1:
    Absolute maximum ratings are those values beyond which the life
    of a device may be impaired.
    Note 2:
    Linearity and monotonicity are defined from code k
    L
    to code
    2
    N
    – 1, where N is the resolution and k
    L
    is given by k
    L
    = 0.016(2
    N
    /V
    REF
    ),
    rounded to the nearest whole code. For V
    REF
    = 4.096V and N = 16,
    k
    L
    = 256 and linearity is defined from code 256 to code 65,535.
    Note 3:
    SDA, SCL at 0V or V
    CC
    , CA0, CA1 and CA2 floating.
    Note 4:
    Inferred from measurement at code 256 (LTC2605/LTC2605-1),
    code 64 (LTC2615/LTC2615-1) or code 16 (LTC2625/LTC2625-1) and
    at full scale.
    Note 5:
    V
    CC
    = 5V, V
    REF
    = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
    and 3/4 scale to 1/4 scale. Load is 2k
    in parallel with 200pF to GND.
    Note 6:
    V
    CC
    = 5V, V
    REF
    = 4.096V. DAC is stepped
    ±
    1LSB between half
    scale and half scale – 1. Load is 2k
    in parallel with 200pF to GND.
    Note 7:
    C
    B
    = capacitance of one bus line in pF.
    Note 8:
    All values refer to V
    IH(MIN)
    and V
    IL(MAX)
    levels.
    Note 9:
    These specifications apply to LTC2605/LTC2605-1, LTC2615/
    LTC2615-1 and LTC2625/LTC2625-1.
    Note 10:
    DC Crosstalk is measured with V
    CC
    = 5V and V
    REF
    = 4096V, with
    the measured DAC at midscale, unless otherwise noted.
    Note 11:
    R
    L
    = 2k
    to GND or V
    CC
    .
    Note 12:
    Guaranteed by design and not production tested.
    ELECTRICAL C
    temperature range, otherwise specifications are at T
    A
    = 25
    °
    C. REF = 4.096V (V
    CC
    = 5V), REF = 2.048V (V
    CC
    = 2.7V), V
    OUT
    unloaded,
    unless otherwise noted.
    HARA TERISTICS
    The
    denotes specifications which apply over the full operating
    LTC2625/-1
    MIN
    TYP
    LTC2615/-1
    MIN
    TYP
    LTC2605/-1
    MIN
    TYP
    SYMBOL
    AC Performance
    t
    S
    PARAMETER
    CONDITIONS
    MAX
    MAX
    MAX
    UNITS
    Settling Time (Note 5)
    ±
    0.024% (
    ±
    1LSB at 12 Bits)
    ±
    0.006% (
    ±
    1LSB at 14 Bits)
    ±
    0.0015% (
    ±
    1LSB at 16 Bits)
    ±
    0.024% (
    ±
    1LSB at 12 Bits)
    ±
    0.006% (
    ±
    1LSB at 14 Bits)
    ±
    0.0015% (
    ±
    1LSB at 16 Bits)
    7
    7
    9
    7
    9
    μ
    s
    μ
    s
    μ
    s
    μ
    s
    μ
    s
    μ
    s
    10
    2.7
    4.8
    5.2
    0.80
    1000
    12
    180
    120
    100
    15
    Settling Time for 1LSB Step
    (Note 6)
    2.7
    2.7
    4.8
    Voltage Output Slew Rate
    Capacitive Load Driving
    Glitch Impulse
    Multiplying Bandwidth
    Output Voltage Noise Density
    0.80
    1000
    12
    180
    120
    100
    15
    0.80
    1000
    12
    180
    120
    100
    15
    V/
    μ
    s
    pF
    nV s
    kHz
    nV/
    Hz
    nV/
    Hz
    μ
    V
    P-P
    At Midscale Transition
    e
    n
    At f = 1kHz
    At f = 10kHz
    0.1Hz to 10Hz
    Output Voltage Noise
    SYMBOL
    V
    CC
    = 2.7V to 5.5V
    f
    SCL
    t
    HD(STA)
    t
    LOW
    t
    HIGH
    t
    SU(STA)
    t
    HD(DAT)
    t
    SU(DAT)
    t
    r
    t
    f
    t
    SU(STO)
    t
    BUF
    PARAMETER
    CONDITIONS
    MIN
    TYP
    MAX
    UNITS
    SCL Clock Frequency
    Hold Time (Repeated) Start Condition
    Low Period of the SCL Clock Pin
    High Period of the SCL Clock Pin
    Set-Up Time for a Repeated Start Program
    Data Hold Time
    Data Set-Up Time
    Rise Time of Both SDA and SCL Signals
    Fall Time of Both SDA and SCL Signals
    Set-Up Time for Stop Condition
    Bus Free Time Between a Stop and Start Condition
    0
    400
    kHz
    μ
    s
    μ
    s
    μ
    s
    μ
    s
    μ
    s
    ns
    ns
    ns
    μ
    s
    μ
    s
    0.6
    1.3
    0.6
    0.6
    0
    100
    0.9
    (Note 7)
    (Note 7)
    20 + 0.1C
    B
    20 + 0.1C
    B
    0.6
    1.3
    300
    300
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