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參數(shù)資料
| 型號(hào)： | LTC2601CDD-1#PBF |
| 廠(chǎng)商： | Linear Technology |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT R-R 10-DFN |
| 標(biāo)準(zhǔn)包裝： | 121 |
| 設(shè)置時(shí)間： | 10µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.88mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 10-DFN（3x3） |
| 包裝： | 管件 |
| 輸出數(shù)目和類(lèi)型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁(yè)面： | 1350 (CN2011-ZH PDF) |
| 配用： | DC777A-ND - BOARD DAC LTC2601 |
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LTC2601/LTC2611/LTC2621
12
2601fb
OPERATION
next device in the chain. The shift registers of the devices
are thus connected in series, effectively forming a single
input shift register which extends through the entire
chain. Because of this, the devices can be addressed and
controlled individually by simply concatenating their input
words; the rst instruction addresses the last device in
the chain and so forth. The SCK and CS/LD signals are
common to all devices in the series.
In use, CS/LD is rst taken low. Then the concatenated
input data is transferred to the chain, using SDI of the
rst device as the data input. When the data transfer is
complete, CS/LD is taken high, which executes the com-
mands specied for each of the devices simultaneously. A
single device can be controlled by using the no-operation
command (1111) for the other devices in the chain.
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever the
DAC output is not needed. When in power-down, the buffer
amplier, bias circuit and reference input is disabled and
draws essentially zero current. The DAC output is put into a
high impedance state, and the output pin is passively pulled
to ground through 90k resistors. Input- and DAC-register
contents are not disturbed during power-down.
The DAC can be put into power-down mode by using
command 0100b. The 16-bit data word is ignored. The
supply and reference currents are reduced to almost zero
when the DAC is powered down; the effective resistance at
REF rises accordingly becoming a high impedance input
(typically > 1GΩ).
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 1 or
performing an asynchronous update (LDAC) as described
in the next section. The DAC is powered up as its voltage
output is updated. When the DAC in powered-down state
is powered up and updated, normal settling is delayed. The
main bias generation circuit block has been automatically
shut down in addition to the DAC amplier and reference
input and so the power up delay time is 12μs (for VCC =
5V) or 30μs (for VCC = 3V).
Asynchronous DAC Update Using LDAC
In addition to the update commands shown in Table 1,
the LDAC pin asynchronously updates the DAC register
with the contents of the input register.
If CS/LD is high, a low on the LDAC pin causes the DAC
register to be updated with the contents of the input
register.
If CS/LD is low, a low going pulse on the LDAC pin before
the rising edge of CS/LD powers up the DAC but does not
cause the output to be updated. If LDAC remains low after
INPUT WORD (LTC2601)
INPUT WORD (LTC2611)
INPUT WORD (LTC2621)
C3
COMMAND
DON’T CARE BITS
DATA (16 BITS)
C2
C1
C0
X
D13
D14
D15
D12 D11 D10 D9
D8
D7 D6
D5
D4
D3
D2
D1 D0
2601 TBL01
MSB
LSB
C3
COMMAND
DON’T CARE BITS
DATA (14 BITS + 2 DON’T CARE BITS)
C2
C1
C0
X
D13 D12 D11 D10 D9
D8
D7 D6
D5
D4
D3
D2
D1 D0
X
2601 TBL02
MSB
LSB
C3
COMMAND
DON’T CARE BITS
DATA (12 BITS + 4 DON’T CARE BITS)
C2
C1
C0
X
D11 D10 D9
D8
D7 D6
D5
D4
D3
D2
D1 D0
X
XX
2601 TBL03
MSB
LSB
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