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參數(shù)資料
| 型號： | LTC2499CUHF#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/34頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT DELTA SIG 38-QFN |
| 標準包裝： | 52 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 38-QFN（5x7） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 16 個單端，雙極；8 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC1012A-A-ND - BOARD DELTA SIGMA ADC LTC2499 |
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LTC2499
2499fd
matches the hard wired LTC2499’s address (one of 27
pin-selectable addresses) the device is selected. When the
device is addressed during the conversion state, it will not
acknowledge R/W requests and will issue a NACK by leav-
ing the SDA line HIGH. If the conversion is complete, the
LTC2499 issues an ACK by pulling the SDA line LOW.
The LTC2499 has two registers. The output register (32
bits long) contains the last conversion result. The input
register (16 bits long) sets the input channel, selects the
temperature sensor, rejection mode, and speed mode.
DATA OUTPUT FORMAT
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters the sleep state where the supply current is
reduced to 1A. When the LTC2499 is addressed for a read
operation, it acknowledges (by pulling SDA LOW) and acts
as a transmitter. The master/receiver can read up to four
bytes from the LTC2499. After a complete read operation
(4 bytes), a new conversion is initiated. The device will
NACK subsequent read operations while a conversion is
being performed.
Table 1. Output Data Format
DIFFERENTIAL INPUT VOLTAGE
VIN*
BIT 31
SIG
BIT 30
MSB
BIT 29
BIT 28
BIT 27
…
BIT 6
LSB
BITs 5-0
Sub LSBs
VIN* ≥ FS**
1
0
…
0
00000
FS** – 1LSB
1
0
1
…
1
XXXXX
0.5 FS**
1
0
1
0
…
0
XXXXX
0.5 FS** – 1LSB
1
0
1
…
1
XXXXX
0
1/0
0
…
0
XXXXX
–1LSB
0
1
…
1
XXXXX
–0.5 FS**
0
1
0
…
0
XXXXX
–0.5 FS** – 1LSB
0
1
0
1
…
1
XXXXX
–FS**
0
1
0
…
0
XXXXX
VIN* < –FS**
0
1
…
1
11111
*The differential input voltage VIN = IN+ – IN–.
**The full-scale voltage FS = 0.5 VREF. Sub LSBs are below the 24-bit level. They may be included in averaging, or discarded without loss of resolution.
The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.
The data output stream is 32 bits long and is shifted out
on the falling edges of SCL (see Figure 3a). The first bit is
the conversion result sign bit (SIG) (see Tables 1 and 2).
This bit is HIGH if VIN ≥ 0 and LOW if VIN < 0 (where VIN
corresponds to the selected input signal IN+ – IN–). The
second bit is the most significant bit (MSB) of the result.
The first two bits (SIG and MSB) can be used to indicate
over and under range conditions (see Table 2). If both bits
are HIGH, the differential input voltage is equal to or above
+FS. If both bits are set LOW, the input voltage is below
–FS. The function of these bits is summarized in Table
2. The 24 bits following the MSB bit are the conversion
result in binary two’s, complement format. The remaining
six bits are sub LSBs below the 24-bit level.
As long as the voltage on the selected input channels (IN+
and IN–) remains between –0.3V and VCC + 0.3V (absolute
maximum operating range) a conversion result is gener-
ated for any differential input voltage VIN from –FS = –0.5
VREF to +FS = 0.5 VREF. For differential input voltages
greater than +FS, the conversion result is clamped to the
value corresponding to +FS. For differential input voltages
below –FS, the conversion result is clamped to the value
–FS – 1LSB.
applications inForMation
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