參數(shù)資料
型號(hào)： LTC2498IUHF#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 9/38頁(yè)
文件大小： 0K
描述： IC ADC 24BIT 16CH 38-QFN
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 38-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 38-QFN（5x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 16 個(gè)單端，雙極；8 個(gè)差分，雙極
配用： DC1011A-A-ND - BOARD DELTA SIGMA ADC LTC2498
LTC2498
17
2498ff
applications inForMation
+FS. If both Bit 29 and Bit 28 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2498 Status Bits
Input Range
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
VIN ≥ 0.5 VREF
0
1
0V ≤ VIN < 0.5 VREF
0
1/0
0
–0.5 VREF ≤ VIN < 0V
0
1
VIN < –0.5 VREF
0
Bits 28 to 5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB24).
Bits 4 to 0 are sub LSBs below the 24-bit level. Bits 4 to
0 may be included in averaging or discarded without loss
of resolution.
Data is shifted out of the SDO pin under control of the
serial clock (SCK), see Figure 3. Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on
the first falling edge of SCK. The final data bit (Bit 0) is
shifted out on the on the falling edge of the 31st SCK and
may be latched on the rising edge of the 32nd SCK pulse.
On the falling edge of the 32nd SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 31) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the IN+ and IN– pins remains be-
tween–0.3VandVCC+0.3V(absolutemaximumoperating
range) a conversion result is generated for any differential
input voltage VIN from –FS = –0.5 VREF to +FS = 0.5
VREF. For differential input voltages greater than +FS, the
conversion result is clamped to the value corresponding
to +FS + 1LSB. For differential input voltages below –FS,
the conversion result is clamped to the value –FS – 1LSB.
Figure 3. Channel Selection, Configuration Selection and Data Output Timing
EOC
CS
SCK
SDI
SDO
2498 F03
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
SIG
BIT 29
“0”
BIT 30
BIT 31
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
ODD
BIT 18 BIT 17
BIT 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
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