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參數(shù)資料
| 型號： | LTC2496IUHF#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 31/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG 38-QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6.9 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 38-QFN（5x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 16 個單端，雙極；8 個差分，雙極 |
| 配用： | DC1011A-B-ND - BOARD DELTA SIGMA ADC LTC2496 |
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LTC2496
2496fb
pin FuncTions
GND (Pins 1, 3, 4, 5, 6, 31, 32, 33): Ground. Multiple
groundpinsinternallyconnectedforoptimumgroundcur-
rent flow and VCC decoupling. Connect each one of these
pins to a common ground plane through a low impedance
connection. All 8 pins must be connected to ground for
proper operation.
NC (Pin 2): No Connection, this pin can be left floating
or tied to GND.
COM (Pin 7): The common negative input (IN–) for all
single-ended multiplexer configurations. The voltage on
CH0 to CH15 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN–) provide a bipolar input range
(VIN = IN+ – IN–) from –0.5 VREF to 0.5 VREF. Outside
thisinputrange,theconverterproducesuniqueover-range
and under-range output codes.
CH0 to CH15 (Pins 8 to 23): Analog Inputs. May be pro-
grammed for single-ended or differential mode.
MUXOUTP (Pin 24): Positive Multiplexer Output. Used
to drive an external buffer/amplifier or can be shorted
directly to ADCINP.
ADCINP (Pin 25): Positive ADC Input. Tie to the output of
a buffer/amplifier driven by MUXOUTP or short directly
to MUXOUTP.
ADCINN (Pin 26): Negative ADC Input. Tie to the output
of a buffer/amplifier driven by MUXOUTN or short directly
to MUXOUTN.
MUXOUTN (Pin 27): Negative Multiplexer Output. Used
to drive an external buffer/amplifier or can be shorted
directly to ADCINN.
VCC(Pin28):PositiveSupplyVoltage.BypasstoGNDwith
a 10F tantalum capacitor in parallel with a 0.1F ceramic
capacitor as close to the part as possible.
REF+(Pin29),REF–(Pin30):DifferentialReferenceInput.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 0.1V. The differential voltage (REF = REF+
– REF–) sets the full-scale range for all input channels.
SDI (Pin 34): Serial Data Input. This pin is used to select
the input channel. The serial data input is applied under
control of the serial clock (SCK) during the data output
operation. The first conversion following a new input is
valid.
fO (Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock rate. When fO is
connected to VCC or GND, the converter uses its internal
oscillator running at 307.2kHz. The conversion clock may
also be overridden by driving the fO pin with an external
clock in order to change the output rate and the digital
filter rejection null.
CS (Pin 36): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output aborts the data transfer and starts
a new conversion.
SDO (Pin 37): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select pin is HIGH, the SDO pin is in a high
impedancestate.Duringtheconversionandsleepperiods,
this pin is used as the conversion status output. When
the conversion is in progress this pin is HIGH; once the
conversion is complete SDO goes low. The conversion
status is monitored by pulling CS LOW.
SCK(Pin38):Bidirectional,DigitalI/O,ClockPin.InInternal
Serial Clock Operation mode, SCK is generated internally
and is seen as an output on the SCK pin. In External Serial
Clock Operation mode, the digital I/O clock is externally
applied to the SCK pin. The Serial Clock operation mode
is determined by the logic level applied to the SCK pin at
power up and during the most recent falling edge of CS.
GND (Exposed Pad Pin 39): Ground. This pin is ground
and must be soldered to the PCB ground plane. For pro-
totyping purposes, this pin may remain floating.
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