參數(shù)資料
型號(hào)： LTC2495CUHF
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 16-Bit 8-/16-Channel ツヒ ADC with PGA, Easy Drive and I2C Interface
中文描述： 16-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC38
封裝： 5 X 7 MM, PLASTIC, MO-220WKHD, QFN-38
文件頁(yè)數(shù)： 21/32頁(yè)
文件大小： 558K
代理商： LTC2495CUHF
LTC2495
21
2495f
Figure 6. Conversion Sequence
Figure 7. Consecutive Reading with the Same Input/Configuration
Table 6. Address Assignment
CA2
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
CA1
LOW
LOW
LOW
HIGH
HIGH
HIGH
FLOAT
FLOAT
FLOAT
LOW
LOW
LOW
HIGH
HIGH
HIGH
FLOAT
FLOAT
FLOAT
LOW
LOW
LOW
HIGH
HIGH
HIGH
FLOAT
FLOAT
FLOAT
CA0
LOW
HIGH
FLOAT
LOW
HIGH
FLOAT
LOW
HIGH
FLOAT
LOW
HIGH
FLOAT
LOW
HIGH
FLOAT
LOW
HIGH
FLOAT
LOW
HIGH
FLOAT
LOW
HIGH
FLOAT
LOW
HIGH
FLOAT
ADDRESS
0010100
0010110
0010101
0100110
0110100
0100111
0010111
0100101
0100100
1010110
1100100
1010111
1110100
1110110
1110101
1100101
1100111
1100110
0110101
0110111
0110110
1000111
1010101
1010100
1000100
1000110
1000101
APPLICATIONS INFORMATION
unchanged from the last value written into the device. If
the device has not been written to since power up, the
configuration is set to the default value. At the end of a
read operation, a new conversion automatically begins.
At the conclusion of the conversion cycle, the next result
may be read using the method described above. If the
conversion cycle is not concluded and a valid address
selects the device, the LTC2495 generates a NAK signal
indicating the conversion cycle is in progress.
Continuous Read/Write
Once the conversion cycle is concluded, the LTC2495 can
be written to and then read from using the Repeated Start
(Sr) command.
Figure 8 shows a cycle which begins with a data Write, a
repeated Start, followed by a Read and concluded with a
Stop command. The following conversion begins after all
24 bits are read out of the device or after a Stop command.
The following conversion will be performed using the newly
programmed data. In cases where the same speed (1x/2x
mode), rejection frequency (50Hz, 60Hz, 50Hz and 60Hz)
and gain is used but the channel is changed, a Stop or
Repeated Start may be issued after the first byte (channel
selection data) is written into the device.
Discarding a Conversion Result and Initiating a New
Conversion with Optional Write
At the conclusion of a conversion cycle, a write cycle
can be initiated. Once the write cycle is acknowledged, a
Stop command will start a new conversion. If a new input
S
ACK
DATA
Sr
DATA TRANSFERRING
P
SLEEP
DATA INPUT/OUTPUT
CONVERSION
CONVERSION
7-BIT ADDRESS
R/W
2495 F05
7-BIT ADDRESS
CONVERSION
CONVERSION
CONVERSION
SLEEP
SLEEP
DATA OUTPUT
DATA OUTPUT
7-BIT ADDRESS
S
S
R
R
ACK
ACK
READ
READ
P
P
2495 F07
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