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參數(shù)資料
| 型號： | LTC2493CDEPBF |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 24-Bit 2-/4-Channel ADC with Easy Drive Input Current Cancellation and I2C Interface |
| 中文描述： | 24位2-/4-Channel ADC，具有易于驅(qū)動的輸入電流取消和I2C接口 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大小： | 588K |
| 代理商： | LTC2493CDEPBF |
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LTC2493
2493fa
connected to the supply through a pull-up resistor. When
the data line is not being driven, it is high. Data on the
I
2
C bus can be transferred at rates up to 100kbits/s in the
standard mode and up to 400kbits/s in the fast mode.
Each device on the I
2
C bus is recognized by a unique
address stored in that device and can operate either as a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when perform-
ing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals
to permit that transfer. Devices addressed by the master
are considered a slave.
The LTC2493 can only be addressed as a slave. Once
addressed, it can receive configuration bits (channel
selection, rejection mode, speed mode) or transmit the
last conversion result. The serial clock line, SCL, is always
an input to the LTC2493 and the serial data line SDA is
bidirectional. The device supports the standard mode and
the fast mode for data transfer speeds up to 400kbits/s.
Figure 2 shows the definition of the I
2
C timing.
The Start and Stop Conditions
A Start (S) condition is generated by transitioning SDA from
high to low while SCL is high. The bus is considered to be
busy after the Start condition. When the data transfer is
finished, a Stop (P) condition is generated by transitioning
SDA from low to high while SCL is high. The bus is free
after a Stop is generated. Start and Stop conditions are
always generated by the master.
When the bus is in use, it stays busy if a Repeated Start
(Sr) is generated instead of a Stop condition. The repeated
Start timing is functionally identical to the Start and is
used for writing and reading from the device before the
initiation of a new conversion.
Data Transferring
After the Start condition, the I
2
C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit.
The master releases the SDA line during the ninth SCL
clock cycle. The slave device can issue an ACK by pulling
SDA low or issue a Not Acknowledge (NAK) by leaving
the SDA line high impedance (the external pull-up resistor
will hold the line high). Change of data only occurs while
the clock line (SCL) is low.
DATA FORMAT
After a Start condition, the master sends a 7-bit address
followed by a read/write (R/W) bit. The R/W bit is 1 for
a read request and 0 for a write request. If the 7-bit ad-
dress matches the hard wired LTC2493’s address (one of
9 pin-selectable addresses) the device is selected. When
the device is addressed during the conversion state, it will
not acknowledge R/W requests and will issue a NAK by
leaving the SDA line high. If the conversion is complete,
the LTC2493 issues an ACK by pulling the SDA line low.
The LTC2493 has two registers. The output register (32
bits long) contains the last conversion result. The input
register (16 bits long) sets the input channel, selects the
temperature sensor, rejection mode, and speed mode.
SDA
SCL
S
Sr
P
S
t
HD(SDA)
t
HD(DAT)
t
SU(STA)
t
SU(STO)
t
SU(DAT)
t
LOW
t
HD(SDA)
t
SP
t
BUF
t
r
t
f
t
r
t
f
t
HIGH
2493 F02
Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I
2
C Bus
applicaTions inForMaTion
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