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參數(shù)資料
| 型號(hào)： | LTC2492IDE#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 32/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT DELTA SIG 14-DFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 14-DFN-EP（4x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，雙極；2 個(gè)差分，雙極 |
| 配用： | DC1009A-A-ND - BOARD DELTA SIGMA ADC LTC2492 |
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LTC2492
5
2492fd
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fEOSC
External Oscillator Frequency Range
(Note 16)
●
10
4000
kHz
tHEO
External Oscillator High Period
●
0.125
100
μs
tLEO
External Oscillator Low Period
●
0.125
100
μs
tCONV_1
Conversion Time for 1x Speed Mode
50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
●
157.2
131
144.1
160.3
133.6
146.9
41036/fEOSC (in kHz)
163.5
136.3
149.9
ms
tCONV_2
Conversion Time for 2x Speed Mode
50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
●
78.7
65.6
72.2
80.3
66.9
73.6
20556/fEOSC (in kHz)
81.9
68.2
75.1
ms
fISCK
Internal SCK Frequency
Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
38.4
fEOSC/8
kHz
DISCK
Internal SCK Duty Cycle
(Notes 10, 17)
●
45
55
%
fESCK
External SCK Frequency Range
(Notes 10, 11, 15)
●
4000
kHz
tLESCK
External SCK Low Period
(Notes 10, 11, 15)
●
125
ns
tHESCK
External SCK High Period
(Notes 10, 11, 15)
●
125
ns
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
●
0.81
0.83
256/fEOSC (in kHz)
0.85
ms
tDOUT_ESCK
External SCK 32-Bit Data Output Time
(Notes 10, 11, 15)
32/fESCK (in kHz)
ms
t1
CS↓ to SDO Low
●
0
200
ns
t2
CS↑ to SDO Hi-Z
●
0
200
ns
t3
CS↓ to SCK↓
Internal SCK Mode
●
0
200
ns
t4
CS↓ to SCK↑
External SCK Mode
●
50
ns
tKQMAX
SCK
↓ to SDO Valid
●
200
ns
tKQMIN
SDO Hold After SCK
↓
(Note 5)
●
15
ns
t5
SCK Set Up Before CS
↓
●
50
ns
t7
SDI Set Up Before SCK
↑
(Note 5)
●
100
ns
t8
SDI Hold After SCK
↑
(Note 5)
●
100
ns
DIGITAL INPUTS AND DIGITAL OUTPUTS The ● denotes the specications which apply over the
full operating temperature range, otherwise specications are at TA = 25°C. (Note 3)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: Unless otherwise specied:
VCC = 2.7V to 5.5V
VREFCM = VREF/2, FS = 0.5VREF
VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2,
where IN+ and IN– are the selected input channels.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless other wise specied.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is dened as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external
oscillator).
Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external
oscillator).
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or
fEOSC = 280kHz ±2% (external oscillator).
Note 10: The SCK can be congured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as a digital input and the
driving clock is fESCK. In the internal SCK mode, the SCK pin is used as a
digital output and the output clock signal during the data output is fISCK.
Note 11: The external oscillator is connected to the fO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses its internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 16: Refer to Applications Information section for performance vs
data rate graphs.
Note 17: The converter in internal SCK mode of operation such that the
SCK pin is used as a digital output.
Note 18: For VCC < 3V, VIH is 2.5V for pin fO.
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