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參數(shù)資料
| 型號： | LTC2492CDE#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO14 |
| 封裝： | 4 X 3 MM, PLASTIC, MO-229WGED-3, QFN-14 |
| 文件頁數(shù)： | 14/36頁 |
| 文件大小： | 652K |
| 代理商： | LTC2492CDE#TR |
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LTC2492
2492fa
External Serial Clock, Single Cycle Operation
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 6).
Theexternalserialclockmodeisselectedduringthepower-
up sequence and on each falling edge of CS. In order to
enter and remain in the external SCk mode of operation,
SCk must be driven LOW both at power up and on each
CS falling edge. If SCk is HIGH on the falling edge of CS,
the device will switch to the internal SCk mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
When the device is in the sleep state, its conversion result
isheldinaninternalstaticshiftregister.Thedeviceremains
in the sleep state until the first rising edge of SCk is seen
while CS is LOW. The input data is then shifted in via the
SDIpinoneachrisingedgeofSCk(includingthefirstrising
edge). The channel selection and converter configuration
mode will be used for the following conversion cycle. If
the input channel or converter configuration is changed
during this I/O cycle, the new settings take effect on the
conversion cycle following the data input/output cycle.
The output data is shifted out the SDO pin on each falling
edge of SCk. This enables external circuitry to latch the
output on the rising edge of SCk. EOC can be latched on
the first rising edge of SCk and the last bit of the conver-
sion result can be latched on the 32nd rising edge of SCk.
On the 32nd falling edge of SCk, the device begins a new
conversion and SDO goes HIGH (EOC = 1) indicating a
conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
applicaTions inFormaTion
Figure 6. External Serial Clock, Single Cycle Operation
Hi-Z
2492 F06
CS
SCK
(EXTERNAL)
SDI
SDO
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
VCC
FO
REF+
REF–
CH0
CH1
CH2
CH3
COM
SCK
SDI
CS
SDO
GND
12
1
13
14
8
9
10
11
7
3
4
6
5
2
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2492
2.7V TO 5.5V
0.1
F
10
F
4-WIRE
SPI INTERFACE
EOC
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
BIT 29
BIT 30
BIT 31
BIT 18 BIT 17
BIT 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
ODD
DON'T CARE
MSB
SIG
“0”
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