參數(shù)資料
型號(hào)： LTC2484IDD#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 17/42頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 10-DFN
標(biāo)準(zhǔn)包裝： 121
位數(shù)： 24
采樣率（每秒）： 6.8
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 10-DFN（3x3）
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 1348 (CN2011-ZH PDF)
配用： DC939A-ND - BOARD DELTA SIGMA ADC LTC2484
LTC2484
24
2484fd
APPLICATIONS INFORMATION
Internal Serial Clock, 3-Wire I/O,
Continuous Conversion
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally gener-
ated serial clock (SCK) signal, see Figure 10. CS may be
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the internal
serial clock timing mode is automatically selected if SCK
is not externally driven LOW (if SCK is loaded such that
the internal pull-up cannot pull the pin HIGH, the external
SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has nished and the device has entered
the low power sleep state. The part remains in the sleep
state a minimum amount of time (1/2 the internal SCK
period) then immediately begins outputting data. The
data input/output cycle begins on the rst rising edge of
SCK and ends after the 32nd rising edge. The input data
is then shifted in via the SDI pin on the rising edge of
SCK (including the rst rising edge) and the output data
is shifted out of the SDO pin on each falling edge of SCK.
The internally generated serial clock is output to the SCK
pin. This signal may be used to shift the conversion result
into external circuitry. EOC can be latched on the rst ris-
ing edge of SCK and the last bit of the conversion result
can be latched on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1) indicating a
new conversion is in progress. SCK remains HIGH during
the conversion.
EN
GS2
GS1
GS0
IM
FA
FB
SPD
SDI*
DON’T CARE
SDO
SCK
(INTERNAL)
CS
LSB
MSB
SIG
BIT 4
BIT 0
IM
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
EOC
BIT 23
DATA OUTPUT
CONVERSION
2484 F10
VCC
fO
VREF
IN+
IN–
SCK
SDI
SDO
CS
GND
210
INT/EXT CLOCK
3
4
5
9
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUT
1μF
2.7V TO 5.5V
LTC2484
3-WIRE
SPI INTERFACE
10k
VCC
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
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