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參數(shù)資料
| 型號(hào)： | LTC2484CDD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 10-DFN |
| 標(biāo)準(zhǔn)包裝： | 121 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN（3x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC939A-ND - BOARD DELTA SIGMA ADC LTC2484 |
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LTC2484
17
2484fd
APPLICATIONS INFORMATION
an external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
may be outside specications but the following conver-
sions will not be affected. If the change occurs during the
data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.
Table 4 summarizes the duration of each state and the
achievable output data rate as a function of fO.
Ease of Use
The LTC2484 data output has no latency, lter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2484 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2484 automatically enters an internal reset
state when the power supply voltage VCC drops below
approximately 2V. This feature guarantees the integrity
of the conversion result and of the serial interface mode
selection.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on reset (POR)
signal with a duration of approximately 4ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2484 starts a normal conversion cycle and
follows the succession of states described in Figure 1. The
Table 4. LTC2484 State Duration
STATE
OPERATING MODE
DURATION
CONVERT
Internal Oscillator
60Hz Rejection
133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode
67ms, Output Data Rate ≤ 15 Readings/s for 2x Speed Mode
50Hz Rejection
160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode
80ms, Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode
50Hz/60Hz Rejection
147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode
73.6ms, Output Data Rate ≤ 13.6 Readings/s for 2x Speed Mode
External Oscillator
fO = External Oscillator
with Frequency fEOSC kHz
(fEOSC/5120 Rejection)
41036/fEOSCs, Output Data Rate ≤ fEOSC/41036 Readings/s for
1x Speed Mode
20556/fEOSCs, Output Data Rate ≤ fEOSC/20556 Readings/s for
2x Speed Mode
SLEEP
As Long As CS = HIGH, After a Conversion is Complete
DATA OUTPUT
Internal Serial Clock
fO = LOW/HIGH
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 0.83ms
(32 SCK Cycles)
fO = External Oscillator with
Frequency fEOSC kHz
As Long As CS = LOW But Not Longer Than 256/fEOSCms
(32 SCK Cycles)
External Serial Clock with
Frequency fSCK kHz
As Long As CS = LOW But Not Longer Than 32/fSCKms
(32 SCK Cycles)
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%)
–12
–8
–4
0
4
8
12
NORMAL
MODE
REJECTION
(dB)
2484 F03
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
Figure 3. LTC2484 Nomal Mode Rejection When
Using an External Oscillator
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