Timing characTerisTics The l denotes the specifi" />
參數(shù)資料
型號(hào)： LTC2483CDD#PBF
廠商： Linear Technology
文件頁數(shù)： 30/34頁
文件大?。?/td> 0K
描述： IC ADC 16BIT I2C 10-DFN
標(biāo)準(zhǔn)包裝： 121
位數(shù)： 16
采樣率（每秒）： 6.8
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 10-DFN（3x3）
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，雙極
產(chǎn)品目錄頁面： 1348 (CN2011-ZH PDF)
配用： DC955A-ND - BOARD DELTA SIGMA ADC LTC2483
LTC2483
2483fc
Timing characTerisTics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fEOSC
External Oscillator Frequency Range
l
10
4000
kHz
tHEO
External Oscillator High Period
l
0.125
100
s
tLEO
External Oscillator Low Period
l
0.125
100
s
tCONV_1
Conversion Time
Simultaneous 50Hz/60Hz
External Oscillator (Note 10)
l
144.1
146.9
41036/fEOSC
149.9
ms
i2c Timing characTerisTics The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 15)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSCL
SCL Clock Frequency
l
0
400
kHz
tHD(SDA)
Hold Time (Repeated) START Condition
l
0.6
s
tLOW
LOW Period of the SCL Clock Pin
l
1.3
s
tHIGH
HIGH Period of the SCL Clock Pin
l
0.6
s
tSU(STA)
Set-Up Time for a Repeated START Condition
l
0.6
s
tHD(DAT)
Data Hold Time
l
0
0.9
s
tSU(DAT)
Data Set-Up Time
l
100
ns
tr
Rise Time for Both SDA and SCL Signals
(Note 14)
l
20 + 0.1CB
300
ns
tf
Fall Time for Both SDA and SCL Signals
(Note 14)
l
20 + 0.1CB
300
ns
tSU(STO)
Set-Up Time for STOP Condition
l
0.6
s
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2, FS = 0.5VREF;
VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: 50Hz fEOSC = 256kHz ±2% (external oscillator).
Note 8: 60Hz fEOSC = 307.2kHz ±2% (external oscillator).
Note 9: Simultaneous 50Hz/60Hz (internal oscillator) or fEOSC = 280kHz
±2% (external oscillator).
Note 10: The external oscillator is connected to the CA0/F0 pin. The
external oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses the internal oscillator.
Note 12: The output noise includes the contribution of the internal
calibration operations.
Note 13: Guaranteed by design and test correlation.
Note 14: CB = capacitance of one bus line in pF.
Note 15: All values refer to VIH(MIN) and VIL(MAX) levels.
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