參數(shù)資料
型號: LTC2482IDD#PBF
廠商: Linear Technology
文件頁數(shù): 20/32頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 10-DFN
標(biāo)準(zhǔn)包裝: 121
位數(shù): 16
采樣率(每秒): 6.8
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 480µW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 10-DFN(3x3)
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)差分,雙極
產(chǎn)品目錄頁面: 1348 (CN2011-ZH PDF)
配用: DC941A-ND - BOARD DELTA SIGMA ADC LTC2482
LTC2482
27
2482fc
APPLICATIONS INFORMATION
degradation in the converter accuracy and linearity. Typical
measured performance curves for output data rates up to
100 readings per second are shown in Figures 19 to 24. In
order to obtain the highest possible level of accuracy from
this converter at output data rates above 20 readings per
second, the user is advised to maximize the power supply
voltage used and to limit the maximum ambient operating
temperature. In certain circumstances, a reduction of the
differential reference voltage may be benecial.
Input Bandwidth
The combined effect of the internal SINC4 digital lter and
of the analog and digital autocalibration circuits deter-
mines the LTC2482 input bandwidth. When the internal
oscillator is used the 3dB input bandwidth is 3.3Hz. If an
external conversion clock generator of frequency fEOSC
is connected to the fO pin, the 3dB input bandwidth is
10.7 10–6 fEOSC.
Due to the complex ltering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a rst order lter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2482 input bandwidth is shown in
Figure 25. When an external oscillator of frequency fEOSC
is used, the shape of the LTC2482 input bandwidth can
be derived from Figure 25 in which the horizontal axis is
scaled by fEOSC/307200.
The conversion noise (600nVRMS typical for VREF = 5V)
can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is 47nV√Hz
for an innite bandwidth source and 64nV√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplication circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is
a high gain, low bandwidth amplier stage followed by a
high bandwidth unity-gain buffer.
When external ampliers are driving the LTC2482, the
ADC input referred system noise calculation can be
simplied by Figure 26. The noise of an amplier driving
the LTC2482 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass lter with a
corner frequency fi. The amplier noise spectral density
is ni. From Figure 26, using fi as the x-axis selector, we
can nd on the y-axis the noise equivalent bandwidth freqi
of the input driving amplier. This bandwidth includes
the band limiting effects of the ADC internal calibration
and ltering. The noise of the driving amplier referred
to the converter input and including all these effects can
be calculated as N = ni √freqi. The total system noise
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
INPUT
SIGNAL
ATTENUATION
(dB)
–3
–2
–1
0
4
2482 F25
–4
–5
–6
1
2
3
5
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
1
INPUT
REFERRED
NOISE
EQUIVALENT
BANDWIDTH
(Hz)
10
0.1
1
10
100
1k
10k
100k
1M
2482 F26
0.1
100
Figure 25. Input Signal Bandwidth Using the Internal Oscillator
Figure 26. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
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