參數(shù)資料
型號(hào)： LTC2480IDD#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 9/42頁(yè)
文件大小： 0K
描述： IC ADC 16BIT 10-DFN
標(biāo)準(zhǔn)包裝： 121
位數(shù)： 16
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 10-DFN（3x3）
包裝： 管件
輸入數(shù)目和類型： 2 個(gè)單端，雙極；1 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 1348 (CN2011-ZH PDF)
配用： DC798B-ND - BOARD DELTA SIGMA ADC LTC2480
LTC2480
2480fd
applicaTions inForMaTion
Output Data Format
The LTC2480 serial output data stream is 24 bits long.
The first 3 bits represent status information indicating
the sign and conversion state. The next 17 bits are the
conversion result, MSB first. The remaining 4 bits indicate
the configuration state associated with the current con-
version result. The third and fourth bit together are also
used to indicate an underrange condition (the differential
input voltage is below –FS) or an overrange condition (the
differential input voltage is above +FS).
In applications where the processor generates 32 clock
cycles, or to remain compatible with higher resolution
converters, the LTC2480’s digital interface will ignore
extra clock edges seen during the next conversion period
after the 24th and output “1” for the extra clock cycles.
Furthermore, CS may be pulled high prior to outputting
all 24 bits, aborting the data out transfer and initiating a
new conversion.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign
indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0,
this bit is LOW.
Bit20(fourthoutputbit)isthemostsignificantbit(MSB)of
the result. This bit in conjunction with bit 21 also provides
the underrange or overrange indication. If both bit 21 and
bit 20 are HIGH, the differential input voltage is above +FS.
If both bit 21 and bit 20 are LOW, the differential input
voltage is below –FS.
The function of these bits is summarized in Table 3.
Table 3. LTC2480 Status Bits
INPUT RANGE
BIT 23
EOC
BIT 22
DMY
BIT 21
SIG
BIT 20
MSB
VIN ≥ 0.5 VREF
0
1
0V ≤ VIN < 0.5 VREF
0
1/0
0
–0.5 VREF ≤ VIN < 0V
0
1
VIN < –0.5 VREF
0
Bits 20-4 are the 16-bit plus sign conversion result MSB
first.
Bits 3-0 are the corresponding configuration bits for the
present conversion result. Bits 3-1 are the gain set bits
and bit 0 is IM (see Figure 2).
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 2). Whenever CS is HIGH,
Table 4. LTC2480 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
VIN*
BIT 23
EOC
BIT 22
DMY
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
…
BIT 4
VIN* ≥ FS**
0
1
0
…
0
FS** – 1LSB
0
1
0
1
…
1
0.5 FS**
0
1
0
1
0
…
0
0.5 FS** – 1LSB
0
1
0
1
…
1
0
1/0***
0
…
0
–1LSB
0
1
…
1
–0.5 FS**
0
1
0
…
0
–0.5 FS** – 1LSB
0
1
0
1
…
1
–FS**
0
1
0
…
0
VIN* < –FS**
0
1
…
1
* The differential input voltage VIN = IN+ – IN–.
** The full-scale voltage FS = 0.5 VREF.
*** The sign bit changes state during the 0 output code when the device is operating in the 2
× speed mode.
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