參數(shù)資料
型號: LTC2480CMS#PBF
廠商: Linear Technology
文件頁數(shù): 16/42頁
文件大小: 0K
描述: IC ADC 16BIT 10-MSOP
標(biāo)準(zhǔn)包裝: 50
位數(shù): 16
采樣率(每秒): 7.5
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
配用: DC798B-ND - BOARD DELTA SIGMA ADC LTC2480
LTC2480
2480fd
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0
if the device is in the sleep state. Independent of CS, the
device automatically enters the low power sleep state once
the conversion is complete.
When the device is in the sleep state, its conversion result
isheldinaninternalstaticshiftregister.Thedeviceremains
in the sleep state until the first rising edge of SCK is seen
while CS is LOW. The input data is then shifted in via the
SDI pin on the rising edge of SCK (including the first rising
edge) and the output data is shifted out of the SDO pin on
each falling edge of SCK. This enables external circuitry
to latch the output on the rising edge of SCK. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 24th rising
edge of SCK. On the 24th falling edge of SCK, the device
begins a new conversion. SDO goes HIGH (EOC = 1)
indicating a conversion is in progress. In applications
where the processor generates 32 clock cycles, or to
remain compatible with higher resolution converters, the
LTC2480’s digital interface will ignore extra clock edges
seen during the next conversion period after the 24th and
outputs “1” for the extra clock cycles.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time
in order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH anytime between the first rising edge and
the 24th falling edge of SCK (see Figure 6). On the rising
edge of CS, the device aborts the data output state and
immediately initiates a new conversion. If the device has
not finished loading the last input bit SPD of SDI by the
time CS is pulled HIGH, the SDI information is discarded
and the previous configuration is kept. This is useful for
systems not requiring all 24 bits of output data, aborting
an invalid conversion cycle or synchronizing the start of
a conversion.
External Serial Clock, 3-Wire I/O
This timing mode utilizes a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or transmission over an isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is con-
cluded typically 4ms after VCC exceeds approximately 2V.
The level applied to SCK at this time determines if SCK
is internal or external. SCK must be driven LOW prior to
the end of POR in order to enter the external serial clock
timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. EOC may be used as an interrupt
to an external controller indicating the conversion result
is ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge
of EOC, the conversion result is loaded into an internal
static shift register. The input data is then shifted in via
the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. EOC can be latched on
the first rising edge of SCK. On the 24th falling edge of
SCK, SDO goes HIGH (EOC = 1) indicating a new con-
version has begun. In applications where the processor
generates 32 clock cycles, or to remain compatible
with higher resolution converters, the LTC2480’s digital
interface will ignore extra clock edges seen during the
next conversion period after the 24th and outputs “1”
for the extra clock cycles.
applicaTions inForMaTion
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