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參數(shù)資料
| 型號： | LTC2453CTS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT DELTA SIG TSOT23-8 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 60 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 薄型，TSOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | DC1266A-A-ND - BOARD DELTA SIGMA ADC LTC2453 |
LTC2453
4
2453fc
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity, VCC = 5V
Integral Nonlinearity, VCC = 3V
Maximum INL vs Temperature
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tCONV
Conversion Time
l
13
16.6
23
ms
fSCL
SCL Clock Frequency
l
0
400
kHz
tHD(SDA)
Hold Time (Repeated) START Condition
l
0.6
s
tLOW
LOW Period of the SCL Pin
l
1.3
s
tHIGH
HIGH Period of the SCL Pin
l
0.6
s
tSU(STA)
Set-Up Time for a Repeated START Condition
l
0.6
s
tHD(DAT)
Data Hold Time
l
0
0.9
s
tSU(DAT)
Data Set-Up Time
l
100
ns
tr
Rise Time for SDA, SCL Signals
(Note 6)
l
20 + 0.1CB
300
ns
tf
Fall Time for SDA, SCL Signals
(Note 6)
l
20 + 0.1CB
300
ns
tSU(STO)
Set-Up Time for STOP Condition
l
0.6
s
tBUF
Bus Free Time Between a Stop and Start Condition
l
1.3
s
tOF
Output Fall Time VIHMIN to VILMAX
Bus Load CB 10pF to
400pF (Note 6)
l
20 + 0.1CB
250
ns
tSP
Input Spike Suppression
l
50
ns
I2C TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V
unless otherwise specified.
VREF = VREF+ – VREF–, VREFCM = (VREF+ + VREF–)/2, FS = VREF+ – VREF–;
VIN = VIN+ – VIN–, –VREF ≤ VIN ≤ VREF; VINCM = (VIN+ + VIN–)/2.
Note 3. Guaranteed by design, not subject to test.
Note 4. Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
Guaranteed by design and test correlation.
Note 5. Input sampling current is the average input current drawn from
the input sampling network while the LTC2453 is converting.
Note 6. CB = capacitance of one bus line in pF.
Note 7. All values refer to VIH(MIN) and VIL(MAX) levels.
Note 8. A positive current is flowing into the DUT pin.
DIFFERENTIAL INPUT VOLTAGE (V)
–5
INL
(LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
3
2453 G01
–3
–1
1
5
2
–4
–2
0
4
VCC = 5V
VREF+ = 5V
VREF– = 0V
TA = –45°C, 25°C, 90°C
DIFFERENTIAL INPUT VOLTAGE (V)
–3
INL
(LSB)
–0.5
0
0.5
0
2
2453 G02
–1.0
–1.5
–2.0
–2
–1
1
1.0
1.5
2.0
3
VCC = 3V
VREF+ = 3V
VREF– = 0V
TA = –45°C, 25°C, 90°C
TEMPERATURE (°C)
–50
0
INL
(LSB)
0.5
1.0
1.5
2.0
–25
0
25
50
2453 G03
75
100
VCC = VREF+ = 5V, 4.1V, 3V
(TA = 25°C, unless otherwise noted)
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