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參數(shù)資料
| 型號(hào)： | LTC2452ITS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 20/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG TSOT23-8 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 60 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 2.4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 薄型，TSOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 配用： | DC1384A-A-ND - BOARD DELTA SIGMA ADC LTC2452 |
LTC2452
7
2452fd
For more information www.linear.com/LTC2452
applicaTions inForMaTion
Figure 2. LTC2452 State Transition Diagram
of data appears at the SDO pin following each falling edge
detected at the SCK input pin and appears from MSB to
LSB. The user can reliably latch this data on every rising
edge of the external serial clock signal driving the SCK
pin (see Figure 3).
The DATA OUTPUT state concludes in one of two different
ways.First,theDATAOUTPUTstateoperationiscompleted
once all 16 data bits have been shifted out and the clock
then goes low. This corresponds to the 16th falling edge
of SCK. Second, the DATA OUTPUT state can be aborted
at any time by a LOW-to-HIGH transition on the CS input.
Following either one of these two actions, the LTC2452 will
entertheCONVERTstateandinitiateanewconversioncycle.
Power-Up Sequence
When the power supply voltage (VCC) applied to the con-
verter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
When VCC rises above this critical threshold, the converter
generates an internal power-on reset (POR) signal for
approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2452 starts a
conversioncycleandfollowsthesuccessionofstatesshown
in Figure 2. The first conversion result following POR is
accurate within the specifications of the device if the power
supply voltage VCC is restored within the operating range
(2.7V to 5.5V) before the end of the POR time interval.
Ease of Use
The LTC2452 data output has no latency, filter settling
delay or redundant results associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog input voltages requires no special actions.
The LTC2452 performs offset calibrations every conver-
sion. This calibration is transparent to the user and has
no effect upon the cyclic operation described previously.
The advantage of continuous calibration is stability of the
ADC performance with respect to time and temperature.
TheLTC2452includesaproprietaryinputsamplingscheme
that reduces the average input current by several orders
DATA OUTPUT
SLEEP
CONVERT
POWER-ON RESET
YES
2452 F02
16TH FALLING
EDGE OF SCK
OR
CS = HIGH?
SCK = LOW
AND
CS = LOW?
NO
YES
NO
started, this operation can not be aborted except by a low
power supply condition (VCC < 2.1V) which generates an
internal power-on reset signal.
After the completion of a conversion, the LTC2452 enters
the SLEEP state and remains there until both the chip
select and serial clock inputs are low (CS = SCK = LOW).
Followingthiscondition,theADCtransitionsintotheDATA
OUTPUT state.
While in the SLEEP state, whenever the chip select input
is pulled high (CS = HIGH), the LTC2452’s power supply
currentisreducedtolessthan200nA.Whenthechipselect
input is pulled low (CS = LOW), and SCK is maintained at a
HIGHlogiclevel,theLTC2452willreturntoanormalpower
consumption level. During the SLEEP state, the result of
the last conversion is held indefinitely in a static register.
Upon entering the DATA OUTPUT state, SDO outputs the
sign (D15) of the conversion result. During this state,
the ADC shifts the conversion result serially through the
SDO output pin under the control of the SCK input pin.
There is no latency in generating this data and the result
corresponds to the last completed conversion. A new bit
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