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參數(shù)資料
| 型號(hào)： | LTC2452CTS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG TSOT23-8 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 60 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 2.4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 薄型，TSOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 配用： | DC1384A-A-ND - BOARD DELTA SIGMA ADC LTC2452 |
LTC2452
15
2452fd
For more information www.linear.com/LTC2452
applicaTions inForMaTion
A 0.1F, high quality, ceramic capacitor in parallel with a
10F ceramic capacitor should be connected between the
REF and GND pins, as close as possible to the package.
The 0.1F capacitor should be placed closest to the ADC.
Driving VIN+ and VIN–
The input drive requirements can best be analyzed using
the equivalent circuit of Figure 16. The input signal VSIG is
connected to the ADC input pins (IN+ and IN–) through an
equivalentsourceresistanceRS.Thisresistorincludesboth
the actual generator source resistance and any additional
optional resistors connected to the input pins. Optional
input capacitors CIN are also connected to the ADC input
pins. This capacitor is placed in parallel with the ADC
input parasitic capacitance CPAR. Depending on the PCB
layout, CPAR has typical values between 2pF and 15pF. In
addition, the equivalent circuit of Figure 16 includes the
converter equivalent internal resistor RSW and sampling
capacitor CEQ.
Therearesomeimmediatetrade-offsinRSandCINwithout
needing a full circuit analysis. Increasing RS and CIN can
give the following benefits:
1) DuetotheLTC2452’sinputsamplingalgorithm,theinput
current drawn by either VIN+ or VIN– over a conversion
cycle is typically 50nA. A high RS CIN attenuates the
high frequency components of the input current, and
RS values up to 1k result in <1LSB error.
Figure 16. LTC2452 Input Drive Equivalent Circuit
2) The bandwidth from VSIG is reduced at the input pins
(IN+, IN–). This bandwidth reduction isolates the ADC
from high frequency signals, and as such provides
simple anti-aliasing and input noise reduction.
3) Switching transients generated by the ADC are attenu-
ated before they go back to the signal source.
4) A large CIN gives a better AC ground at the input pins,
helping reduce reflections back to the signal source.
5) Increasing RS protects the ADC by limiting the current
during an outside-the-rails fault condition.
There is a limit to how large RS CIN should be for a given
application. Increasing RS beyond a given point increases
the voltage drop across RS due to the input current,
to the point that significant measurement errors exist.
Additionally, for some applications, increasing the RSCIN
product too much may unacceptably attenuate the signal
at frequencies of interest.
For most applications, it is desirable to implement CIN as
a high-quality 0.1F ceramic capacitor and RS ≤ 1k. This
capacitor should be located as close as possible to the
actualVINpackagepin.Furthermore,theareaencompassed
by this circuit path, as well as the path length, should be
minimized.
ILEAK
RSW
15k
(TYP)
ICONV
CIN
IN+
VCC
SIG+
SIG–
RS
CEQ
0.35pF
(TYP)
CPAR
+–
2452 F16
ILEAK
RSW
15k
(TYP)
ICONV
CIN
IN–
VCC
RS
CEQ
0.35pF
(TYP)
CPAR
+–
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