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參數(shù)資料
| 型號： | LTC2451ITS8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | PLASTIC, MO-193, TSOT-23, 8 PIN |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 221K |
| 代理商： | LTC2451ITS8 |
LTC2451
9
2451fd
for all input voltages greater than the voltage correspond-
ing to output code 65535, the converter will generate the
output code 65535.
I2C INTERFACE
The LTC2451 communicates through an I2C interface. The
I2C interface is a 2-wire open-drain interface supporting
multiple devices and masters on a single bus. The con-
nected devices can only pull the data line (SDA) low and
never drive it high. SDA is externally connected to the
supply through a pull-up resistor. When the data line is
free, it is pulled high through this resistor. Data on the I2C
bus can be transferred at rates up to 100k/s in the standard
mode and up to 400k/s in the fast mode.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate either as
a transmitter or receiver, depending on the function of
the device. In addition to transmitters and receivers,
devices can also be considered as masters or slaves when
performing data transfers. A master is the device which
initiates a data transfer on the bus and generates the
clock signals to permit that transfer. Devices addressed
by the master are considered a slave. The address of the
LTC2451 is 0010100.
The LTC2451 can only be addressed as a slave. It can only
transmit the last conversion result. The serial clock line,
SCL, is always an input to the LTC2451 and the serial data
line, SDA, is bidirectional. Figure 2 shows the denition
of the I2C timing.
The Start and Stop Conditions
A Start (S) condition is generated by transitioning SDA from
high to low while SCL is high. The bus is considered to be
busy after the Start condition. When the data transfer is
nished, a Stop (P) condition is generated by transitioning
SDA from low to high while SCL is pulled high. The bus is
free after a Stop is generated. Start and Stop conditions
are always generated by the master.
When the bus is in use, it stays busy if a Repeated Start
(Sr) is generated instead of a Stop condition. The Re-
peated Start (Sr) conditions are functionally identical to
the Start (S).
Data Transferring
After the Start condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit.
The master releases the SDA line during the ninth SCL
clock cycle. The slave device can issue an ACK by pulling
SDA low or issue a Not Acknowledge (NAK) by leaving
the SDA line high impedance (the external pull-up resistor
will hold the line high). Change of data only occurs while
the clock line (SCL) is low.
Data Format
After a Start condition, the master sends a 7-bit address
(factory set at 0010100), followed by a Read request (R)
or Write request (W) bit. The bit R is 1 for a Read request
and 0 for a Write request. If the 7-bit address agrees with
the LTC2451’s address, the device is selected. When the
device is addressed during the conversion state, it does
not accept the request and issues a NAK by leaving the
SDA line high. If the conversion is complete, the LTC2451
issues an ACK by pulling the SDA line low.
The user can send one byte of data into the LTC2451 fol-
lowing a Write request and an ACK. The sequence is shown
in Figure 3. The Write sequence is used solely to set the
APPLICATIONS INFORMATION
Figure 2. Denition of Timing for Fast/Standard Mode Devices on the I2C Bus
SDA
SCL
SSr
P
S
tHD(STA)
tHD(DAT)
tSU(STA)
tSU(STO)
tSU(DAT)
tLOW
tHD(SDA)
tSP
tBUF
tr
tf
tr
tf
tHIGH
2451 F02
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