參數資料
型號： LTC2449I
廠商： Linear Technology Corporation
英文描述： 24-Bit High Speed 8-/16-Channel ADCs with Selectable Speed/Resolution
中文描述： 24位ADC的高速8-/16-Channel可選速度/分辨率
文件頁數： 5/28頁
文件大?。?/td> 270K
代理商： LTC2449I
LTC2444/LTC2445/
LTC2448/LTC2449
5
sn2444589 2444589fs
SYMBOL
D
ISCK
f
ESCK
t
LESCK
t
HESCK
t
DOUT_ISCK
PARAMETER
Internal SCK Duty Cycle
External SCK Frequency Range
External SCK Low Period
External SCK High Period
Internal SCK 32-Bit Data Output Time
CONDITIONS
(Note 9)
(Note 8)
(Note 8)
(Note 8)
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
(Note 8)
(Note 12)
(Note 12)
(Note 9)
(Notes 8, 12)
MIN
45
TYP
MAX
55
20
UNITS
●
%
●
MHz
ns
ns
μ
s
●
25
25
41.6
●
●
●
35.3
30.9
320/f
EOSC
32/f
ESCK
s
s
t
DOUT_ESCK
t
1
t
2
t
3
t
4
t
KQMAX
t
KQMIN
t
5
t
6
t
7
t
8
External SCK 32-Bit Data Output Time
CS
↓
to SDO Low Z
CS
↑
to SDO High Z
CS
↓
to SCK
↓
CS
↓
to SCK
↑
SCK
↓
to SDO Valid
SDO Hold After SCK
↓
SCK Set-Up Before CS
↓
SCK Hold After CS
↓
SDI Setup Before SCK
↑
SDI Hold After SCK
↑
●
●
0
0
25
25
ns
ns
μ
s
ns
ns
ns
ns
ns
ns
ns
●
5
●
25
●
25
(Note 5)
●
15
50
●
●
50
(Note 5)
(Note 5)
●
10
10
●
The
●
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
°
C. (Note 3)
TI I G CHARACTERISTICS
W
U
GND (Pins 1, 4, 5, 6, 31, 32, 33):
Ground. Multiple
ground pins internally connected for optimum ground
current flow and V
CC
decoupling. Connect each one of
these pins to a common ground plane through a low
impedance connection. All 7 pins must be connected to
ground for proper operation.
BUSY (Pin 2):
Conversion in Progress Indicator. This pin
is HIGH while the conversion is in progress and goes LOW
indicating the conversion is complete and data is ready. It
remains LOW during the sleep and data output states. At
the conclusion of the data output state, it goes HIGH
indicating a new conversion has begun.
EXT (Pin 3):
Internal/External SCK Selection Pin. This pin
is used to select internal or external SCK for outputting/
inputting data. If EXT is tied low, the device is in the
external SCK mode and data is shifted out of the device
under the control of a user applied serial clock. If EXT is
tied high, the internal serial clock mode is selected. The
device generates its own SCK signal and outputs this on
the SCK pin. A framing signal BUSY (Pin 2) goes low
indicating data is being output.
COM (Pin 7):
The common negative input (IN
–
) for all
single ended multiplexer configurations. The voltage on
CH0-CH15 and COM pins can have any value between
PIU
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2:
All voltage values are with respect to GND.
Note 3:
V
CC
= 4.5V to 5.5V unless otherwise specified.
V
REF
= REF
+
– REF
–
, V
REFCM
= (REF
+
+ REF
–
)/2;
V
IN
= IN
+
– IN
–
, V
INCM
= (IN
+
+ IN
–
)/2.
Note 4:
F
O
pin tied to GND or to external conversion clock source with
f
EOSC
= 10MHz unless otherwise specified.
Note 5:
Guaranteed by design, not subject to test.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7:
The converter uses the internal oscillator.
Note 8:
The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is f
ESCK
and is expressed in Hz.
Note 9:
The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output. In this mode of operation, the SCK pin
has a total equivalent load capacitance of C
LOAD
= 20pF.
Note 10:
The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in Hz.
Note 11:
The converter uses the internal oscillator. F
O
= 0V.
Note 12:
Guaranteed by design and test correlation.
Note 13:
There is an internal reset that adds an additional 1
μ
s (typ) to the
conversion time.
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