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參數(shù)資料
| 型號： | LTC2442IG |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 24-Bit High Speed 4-Channel Delta-Sigma ADC with Integrated Amplifi er |
| 中文描述： | 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO36 |
| 封裝： | 5.30 MM, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 392K |
| 代理商： | LTC2442IG |
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LTC2442
19
2442f
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and control
the state of the conversion cycle, see Figure 7.
In order to select the internal serial clock timing mode,
the EXT pin must be tied HIGH.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state. Alterna-
tively, BUSY (Pin 2) may be used to monitor the status
of the conversion in progress. BUSY is HIGH during the
conversion and goes LOW at the conclusion. It remains
LOW until the result is read from the device.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit the sleep state and enter the data
output state if CS remains LOW. In order to prevent the
device from exiting the sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
EOCtest
after the falling edge of CS
(if EOC = 0) or t
EOCtest
after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of t
EOCtest
is
500ns. If CS is pulled HIGH before time t
EOCtest
, the device
remains in the sleep state. The conversion result is held
in the internal static shift register.
APPLICATIU
W
U
U
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
BIT 20 BIT 19
BIT 0
LSB
Hi-Z
2442 F07
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z
CS
SCK
SDI
SDO
BUSY
BIT 31
1
0
EN
SGL
0
0
A0
OSR3
OSR2
OSR1
OSR0
TWOX
ODD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
TEST EOC
TEST EOC
DON'T CARE
DON'T CARE
<t
EOC(TEST)
V
CC
V
+
+INA
MUXOUTA
BUSY
SDO
SDI
EXT
SCK
F
O
MUXOUTB
+INB
GND
21
6
7
8
9
28
12
13
11
17
18
10
26
25
4, 5, 32
19
27
2
34
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
24
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE
1
μ
F
0.1
μ
F
4.5V TO 5.5V
V
CC
TO 15V
LTC2442
1
μ
F
0.1
μ
F
CS
4-WIRE
SPI INTERFACE
–15V TO GND
V
–
REF
+
REF
–
OUTB
–INB
ADCINB
CH0
CH1
CH2
CH3
COM
29
30
31
3
33
1
36
35
OUTA
–INA
ADCINA
V
CC
Figure 7. Internal Serial Clock, Single Cycle Operation
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