參數(shù)資料
型號(hào)： LTC2442
廠商： Linear Technology Corporation
英文描述： 24-Bit High Speed 4-Channel Delta-Sigma ADC with Integrated Amplifi er
中文描述： 24位高速4通道Δ-ΣADC的呃綜合擴(kuò)增
文件頁(yè)數(shù)： 30/32頁(yè)
文件大小： 392K
代理商： LTC2442
LTC2442
30
2442f
The amplifiers take approximately 50μs to settle for a
full-scale input voltage. This does not affect accuracy in
either 2x mode or 1x mode for OSR values between 256
to 32768. However, the amplifier settling time will cause
a gain error in 1x mode for OSR values between 64 to
256. This is because the mid-conversion slew time is a
significant portion of the total conversion time. Figure 22
shows the details of a conversion in 1x mode, OSR128,
with a full-scale input voltage applied (V
IN
= 2.5V, V
CM
=
2.5V). The previously selected channel had both inputs
grounded. On the 13
th
falling clock edge, the amplifiers
APPLICATIU
W
U
U
Figure 22. Details of Conversion in 1x Mode, OSR128 (OUTA and OUTB Superimposed)
Figure 23. Details of Conversion in 2x Mode, OSR128 (OUTA and OUTB Superimposed)
begin slewing and have reached the correct voltage before
the conversion begins. Midway through the conversion,
the multiplexer reverses the inputs. Figure 23 shows
operation in 2x mode. After the first half-conversion
is done, the multiplexer reverses. Waiting 50μs before
beginning the next half-conversion allows the amplifiers
to settle fully. 2x mode is recommended for OSR values
between 64 and 128 because the amplifiers have time to
settle between half conversions. If only the 1x data rate
is required, ignore every other sample.
OUTB
BUSY
SCK
CS
OUTB
BUSY
SCK
CS
200μs/DIV
1V/DIV
5V/DIV
200μs/DIV
1V/DIV
5V/DIV
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
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