參數(shù)資料
型號: LTC2440IGN#TR
廠商: Linear Technology
文件頁數(shù): 15/28頁
文件大?。?/td> 0K
描述: IC CONV A/D 24-BIT DIFF 16-SSOP
標準包裝: 2,500
位數(shù): 24
采樣率(每秒): 3.5k
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 40mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,雙極
配用: DC570A-ND - BOARD DELTA SIGMA ADC LTC2440
LTC2440
22
2440fd
APPLICATIONS INFORMATION
LTC2440 Input Structure
Modern delta sigma converters have switched capacitor
front ends that repeatedly sample the input voltage over
some time period. The sampling process produces a small
current pulse at the input and reference terminals as the
capacitors are charged. The LTC2440 switches the input
and reference to a 5pF sample capacitor at a frequency
of 1.8MHz. A simplied equivalent circuit is shown in
Figure 16.
The average input and reference currents can be expressed
in terms of the equivalent input resistance of the sample
capacitor, where:
Req = 1/(fSW Ceq)
When using the internal oscillator, fSW is 1.8MHz and the
equivalent resistance is approximately 110kΩ.
Driving the Input and Reference
Because of the small current pulses, excessive lead length
at the analog or reference input may allow reections or
ringing to occur, affecting the conversion accuracy. The
key to preserving the accuracy of the LTC2440 is complete
settling of these sampling glitches at both the input and
reference terminals. There are several recommended
methods of doing this.
Figure 15. Reduced Power Timing Mode
Figure 16. LTC2440 Input Structure
SLEEP
CONVERT
SLEEP
CONVERT
SLEEP
8mA
2440 F15
8μA
8mA
8μA
DATA
OUT
DATA
OUT
CONVERTER
STATE
SUPPLY
CURRENT
CS
VREF+
VIN+
VCC
RSW (TYP)
500Ω
ILEAK
VCC
ILEAK
VCC
RSW (TYP)
500Ω
CEQ
5pF
(TYP)
(CEQ = 3.5pF SAMPLE CAP + PARASITICS)
RSW (TYP)
500Ω
ILEAK
IIN+
VIN
IIN
IREF+
IREF
2440 F16
ILEAK
VCC
ILEAK
SWITCHING FREQUENCY
fSW = 1.8MHz INTERNAL OSCILLATOR
fSW = fEOSC/5 EXTERNAL OSCILLATOR
VREF
RSW (TYP)
500Ω
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