參數(shù)資料
型號： LTC2439-1
廠商： Linear Technology Corporation
元件分類： ADC
英文描述： 8-/16-Channel 16-Bit No Latency Delta-Sigma ADC
中文描述： 8-/16-Channel 16位無延遲增量累加模數(shù)轉(zhuǎn)換器
文件頁數(shù)： 5/28頁
文件大?。?/td> 288K
代理商： LTC2439-1
LTC2439-1
5
24391f
SYMBOL
f
EOSC
t
HEO
t
LEO
t
CONV
PARAMETER
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time
CONDITIONS
MIN
2.56
0.25
0.25
143.8
TYP
MAX
2000
390
390
149.6
UNITS
kHz
G
G
μ
s
μ
s
ms
ms
kHz
kHz
%
kHz
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
G
F
O
= 0V
External Oscillator (Note 10)
Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
(Note 9)
(Note 8)
(Note 8)
(Note 8)
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
(Note 7)
G
G
146.7
20510/f
EOSC
(in kHz)
17.5
f
EOSC
/8
f
ISCK
Internal SCK Frequency
D
ISCK
f
ESCK
t
LESCK
t
HESCK
t
DOUT_ISCK
Internal SCK Duty Cycle
External SCK Frequency Range
External SCK Low Period
External SCK High Period
Internal SCK 19-Bit Data Output Time
G
45
55
2000
G
G
250
250
1.06
G
G
G
1.09
1.11
152/f
EOSC
(in kHz)
19/f
ESCK
(in kHz)
t
DOUT_ESCK
t
1
t2
t3
t4
t
KQMAX
t
KQMIN
t
5
t
6
t
7
t
8
External SCK 19-Bit Data Output Time
CS
↓
to SDO Low
CS
↑
to SDO High Z
CS
↓
to SCK
↓
CS
↓
to SCK
↑
SCK
↓
to SDO Valid
SDO Hold After SCK
↓
SCK Set-Up Before CS
↓
SCK Hold After CS
↓
SDI Setup Before SCK
↑
SDI Hold After SCK
↑
G
G
0
0
0
200
200
200
G
(Note 9)
(Note 8)
G
G
50
G
220
(Note 5)
G
15
50
G
G
50
(Note 5)
(Note 5)
G
100
100
G
The
G
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
°
C. (Note 3)
TI I G CHARACTERISTICS
U
W
Note 1:
Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2:
All voltage values are with respect to GND.
Note 3:
V
CC
= 2.7V to 5.5V unless otherwise specified.
V
REF
= REF
+
– REF
–
, V
REFCM
= (REF
+
+ REF
–
)/2; V
IN
= IN
+
– IN
–
,
V
INCM
= (IN
+
+ IN
–
)/2, IN
+
and IN
–
are defined as the selected positive
and negative input respectively.
Note 4:
F
O
pin tied to GND or to V
CC
or to external conversion clock
source with f
EOSC
= 153600Hz unless otherwise specified.
Note 5:
Guaranteed by design, not subject to test.
Note 6:
Integral nonlinearity is defined as the deviation of a code from
a precise analog input voltage. Maximum specifications are limited by
the LSB step size (V
REF
/2
16
) and the single shot measurement. Typical
specifications are measured from the center of the quantization band.
Note 7:
F
O
= GND (internal oscillator) or f
EOSC
= 139800Hz
±
2%
(external oscillator).
Note 8:
The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is f
ESCK
and is expressed in kHz.
Note 9:
The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance C
LOAD
= 20pF.
Note 10:
The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in kHz.
Note 11:
The converter uses the internal oscillator.
F
O
= 0V or F
O
= V
CC
.
Note 12:
1
μ
V RMS noise is independent of V
REF
. Since the noise
performance is limited by the quantization, lowering V
REF
improves the
effective resolution.
Note 13:
Guaranteed by design and test correlation.
Note 14:
The low sleep mode current is valid only when CS is high.
Note 15:
These parameters are guaranteed by design over the full
supply and temperature range. Automated testing proceedures are
limited by the LSB Step Size (V
REF
/2
16
).
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